• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.449-452
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• 1998

In this study, the basic image-board and algorithm has been developed to extract a road lane by modeling the driving process. The high speed processing enables an image capture, processing and prompt decision making. In order to high speed processing ASIC like FPGA was designed and integrated in one board system. The algorithm enabling road driving must recognize a straight and bend edge separately. The high speed image processing board using FPGA can be used in real-time decision makeing system for road driving and in the machine vision under bad working environments like a coal mine. And it also can be used in the safety control system in subway and in image input system of CCTV and CATV by designing the board to meet various user's needs.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.133-134
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• 2007

The effective data processing mechanism in the sensor network means data stream model and real-time query processing model for real-time processing of stream data. This mechanism can improve satisfaction of users and reduce delay rate of data processing. In this paper, we explain the problem which is occurred when users need to search certain information among information of stream data and describe reduction model of delay rate according to data transmission.

• Korean Journal of Remote Sensing
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• v.9 no.1
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• pp.37-49
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• 1993

In this research, the WEF AX and APT(Automatic Picture Transmission) data receiving and image processing software using PC/AT called WADIPS(WEFAX and APT Data Integrated Processing System) Software has been developed. The main functions of WADIPS software are follow : 1) Real time receiving and saving to hard disk of WEFAX and APT data 2) B/W(Black and White) and false color display 3) Image enhancement using histogram stretch and color control 4) 2-4 times zooming 5) Hard copy of data using dithering and patterning 6) Animation 7) File management 8) On line help. WADIPS can be used in the offices or persons need real time meteorological information and education offices to teach the image processing technique and general characteristics of meteorological satellites.

• The KIPS Transactions:PartD
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• v.11D no.3
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• pp.709-716
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• 2004

This paper describes an intelligent real-time monitoring system of a semiconductor processing equipment, which determines normal or not for a wafer in processing, using multiple time-series pattern recognition. The proposed system consists of three phases, initialization, learning and real-time prediction. The initialization phase sets the weights and tile effective steps for all parameters of a monitoring equipment. The learning phase clusters time series patterns, which are producted and fathered for processing wafers by the equipment, using LBG algorithm. Each pattern has an ACI which is measured by a tester at the end of a process The real-time prediction phase corresponds a time series entered by real-time with the clustered patterns using Dynamic Time Warping, and finds the best matched pattern. Then it calculates a predicted ACI from a combination of the ACI, the difference and the weights. Finally it determines Spec in or out for the wafer. The proposed system is tested on the data acquired from etching device. The results show that the error between the estimated ACI and the actual measurement ACI is remarkably reduced according to the number of learning increases.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.10
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• pp.3989-4006
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• 2020

The intelligent agriculture monitoring is based on the perception and analysis of environmental data, which enables the monitoring of the production environment and the control of environmental regulation equipment. As the scale of the application continues to expand, a large amount of data will be generated from the perception layer and uploaded to the cloud service, which will bring challenges of insufficient bandwidth and processing capacity. A fog-based offline and real-time hybrid data analysis architecture was proposed in this paper, which combines offline and real-time analysis to enable real-time data processing on resource-constrained IoT devices. Furthermore, we propose a data process-ing algorithm based on the incremental principal component analysis, which can achieve data dimensionality reduction and update of principal components. We also introduce the concept of Squared Prediction Error (SPE) value and realize the abnormal detection of data through the combination of SPE value and data fusion algorithm. To ensure the accuracy and effectiveness of the algorithm, we design a regular-SPE hybrid model update strategy, which enables the principal component to be updated on demand when data anomalies are found. In addition, this strategy can significantly reduce resource consumption growth due to the data analysis architectures. Practical datasets-based simulations have confirmed that the proposed algorithm can perform data fusion and exception processing in real-time on resource-constrained devices; Our model update strategy can reduce the overall system resource consumption while ensuring the accuracy of the algorithm.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.2
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• pp.193-199
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• 2008

In this paper, it is proposed the implementation of face authentication system based on real-time image processing. We described the process implementing the two steps for real-time face authentication system. At first face detection steps, we describe the face detection by using feature of wavelet transform, LoG operator and hausdorff distance matching. In the second step we describe the new dual-line principal component analysis(PCA) for real-time face recognition. It is combines horizontal line to vertical line so as to accept local changes of PCA. The proposed system is affected a little by the video size and resolution. And then simulation results confirm the effectiveness of out system and demonstrate its superiority to other conventional algorithm. Finally, the possibility of performance evaluation and real-time processing was confirmed through the implementation of face authentication system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.2
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• pp.13-19
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• 2012

The techniques of 3d image processing have broadly used in the areas including movies, games, performances, exhibitions. In addition, increasing demands for practical uses have gradually extended to the areas of architecture, medicine, nuclear power plant. However, dominant techniques for 3d image processing seem to depend on multi-camera in which two stereo images are merged into one image. Also the pipeline has limitations to provide real-time 3d viewer in ubiquitous computing. It is not able to be applicable onto most general screens as well. In addition, the techniques can be utilized for the real-time 3d game play without a particular monitor or convertor. Hence, the research presented here is to aim at developing an efficient real-time 3d viewer using only mono camera which do not need post processing for editing as well.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.100-105
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• 2009

A watermarking for copyright protection of digital contents for broadcasting have to be made for a real-time system. In this paper, we propose a real-time video watermarking chip and system which is hardware based watermark embedding system of SD/HD video. Our chip is implemented by FPGA which is STRATIX device from ALTERA, and our system is implemented by GS1560A and GS1532 devices from GENNUM for HD/SD video signal processing. There was little visual artifact due to watermarking in subjective quality evaluation between the original video and the watermarked one. Embedded watermark was all extracted after a robustness test called natural video attacks such as A/D conversion and MPEG compression. Our implemented watermarking hardware system can be useful in movie production and broadcasting companies that requires real-time based copyright protection system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.2
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• pp.20-25
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• 2021

The target-object classification method was implemented using a deep-learning-based detection model in real-time images. The object detection model was a deep-learning-based detection model that allowed extensive data collection and machine learning processes to classify similar target-objects. The recognition model was implemented by changing the processing structure of the detection model and combining developed the vision-processing module. To classify the target-objects, the identity and similarity were defined and applied to the detection model. The use of the recognition model in industry was also considered by verifying the effectiveness of the recognition model using the real-time images of an actual soccer game. The detection model and the newly constructed recognition model were compared and verified using real-time images. Furthermore, research was conducted to optimize the recognition model in a real-time environment.