• Journal of Korea Multimedia Society
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• v.24 no.4
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• pp.538-549
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• 2021

In this paper, we introduce a technique for 360-degree panoramic video streaming with multiple virtual cameras in real-time. The proposed technique consists of generating 360-degree panoramic video data by ORB feature point detection, texture transformation, panoramic video data compression, and RTSP-based video streaming transmission. Especially, the generating process of 360-degree panoramic video data and texture transformation are accelerated by CUDA for complex processing such as camera calibration, stitching, blending, encoding. Our experiment evaluated the frames per second (fps) of the transmitted 360-degree panoramic video. Experimental results verified that our technique takes at least 30fps at 4K output resolution, which indicates that it can both generates and transmits 360-degree panoramic video data in real time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.7
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• pp.3543-3557
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• 2017

Compression is a very important technique for remotely sensed hyperspectral images. The lossless compression based on the recursive least square (RLS), which eliminates hyperspectral images' redundancy using both spatial and spectral correlations, is an extremely powerful tool for this purpose, but the relatively high computational complexity limits its application to time-critical scenarios. In order to improve the computational efficiency of the algorithm, we optimize its serial version and develop a new parallel implementation on graphics processing units (GPUs). Namely, an optimized recursive least square based on optimal number of prediction bands is introduced firstly. Then we use this approach as a case study to illustrate the advantages and potential challenges of applying GPU parallel optimization principles to the considered problem. The proposed parallel method properly exploits the low-level architecture of GPUs and has been carried out using the compute unified device architecture (CUDA). The GPU parallel implementation is compared with the serial implementation on CPU. Experimental results indicate remarkable acceleration factors and real-time performance, while retaining exactly the same bit rate with regard to the serial version of the compressor.

• Transactions of Materials Processing
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• v.12 no.2
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• pp.110-115
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• 2003

This paper is concerned with the compression test and forming process of flange by using virtual reality and analysis(simulation) program. This virtual manufacturing can be carried out one personal computer without any expensive devices for experiment. The virtual manufacturing composed of three modules such as the imput, calculation and the output modules on internet. Internet user can give the material's property and process parameters to the sever computer at the input module. On the calculation module, a simulator computes the virtual manufacturing process by analysis program and stores the data as a file. The output module is the program in which internet user can confirm virtual manufacturing results by showing tables, graphs, and 3D animation. This programs is designed by an internet language such as HTML, CGI, VRML and JAVA ,while analysis programs use the finite increasing, the virtual manufacturing technique will substitute many real experiments in the future.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.167-176
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• 2012

In this paper we design and implement a new Hybrid Equipment Data Acquisition System (HEDAS) for data collection of semiconductor and optoelectronic manufacturing equipments in the equipment engineering system(EES) framework. The amount of the data collected from equipments have increased rapidly in equipment engineering system. The proposed HEDAS efficiently handles a large amount of real-time equipment data generated from EES framework. It also can support the real-time ESS applications as well as non real-time ESS applications. For the real-time EES applications, it performs high-speed real-time processing that uses continuous query and filtering techniques based on memory buffers. The HEDAS can optionally store non real-time equipment data using a HEDAS-based database or a traditional DBMS-based database. In particular, The proposed HEDAS offers the compression indexing based on the timestamp of data and query processing technique saving the cost of disks storage against extremely increasing equipment data. The HEDAS is efficient system to collect huge real-time and non real-time equipment data and transmit the collected equipment data to several EES applications in EES framework.

• 한국공간정보시스템학회:학술대회논문집
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• 2005.05a
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• pp.221-224
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• 2005

• Proceedings of the Korean Information Science Society Conference
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• 2001.04b
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• pp.541-543
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• 2001

본 연구에서는 1비트 단위로 연속적으로 입력되는 수표의 영상데이터를 실시간으로 압축처리하고 또한 수표의 하단부에 기록된 인식하기 위한 알고리즘과 하드웨어 구현을 보여준다. 제안된 알고리즘에서는 실시간 처리를 위해 하드웨어에 적합한 알고리즘이 소개되며, 실제로 PLD로 설계 구현하여 그 타당성을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.4
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• pp.1457-1470
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• 2015

In wireless multimedia sensor networks (WMSN), the latency of transmission is an increasingly problem. With the improvement of resolution, the time cost in image and video compression is more and more, which seriously affects the real-time of WMSN. In JPEG system, the core of the system is DCT, but DCT-JPEG is not the best choice. Block-based DCT transform coding has serious blocking artifacts when the image is highly compressed at low bit rates. APBT is used in this paper to solve that problem, but APBT does not have a fast algorithm. In this paper, we analyze the structure in JPEG and propose a parallel framework to speed up the algorithm of JPEG on GPU. And we use all phase biorthogonal transform (APBT) to replace the discrete cosine transform (DCT) for the better performance of reconstructed image. Therefore, parallel APBT-JPEG is proposed to solve the real-time of WMSN and the blocking artifacts in DCT-JPEG in this paper. We use the CUDA toolkit based on GPU which is released by NVIDIA to design the parallel algorithm of APBT-JPEG. Experimental results show that the maximum speedup ratio of parallel algorithm of APBT-JPEG can reach more than 100 times with a very low version GPU, compared with conventional serial APBT-JPEG. And the reconstructed image using the proposed algorithm has better performance than the DCT-JPEG in terms of objective quality and subjective effect. The proposed parallel algorithm based on GPU of APBT also can be used in image compression, video compression, the edge detection and some other fields of image processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10B
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• pp.919-927
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• 2008

The growing availability of broadband multimedia applications are providing strict real-time services and enabling users to feel much interactivity as well as 'sense of presence'. In that sense, there would be increased demand for what network and system have to do to fulfill the user expectations. In this paper, we implement a real-time multimedia application which make use of real-time DXT CODEC and investigate what the challenges of networking and system are. We carry out various experiments over a research network test-bed to evaluate the performance of our proposals.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1107-1111
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• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.37-44
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• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.