• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.866-874
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• 2006

This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10B
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• pp.1200-1209
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• 2011

In this paper, we propose a novel energy efficient MAC protocol which is based on orthogonal frequency division multiple access (OFDMA) and exploits the physical characteristic that propagation loss of acoustic wave depends on the distance. In the proposed scheme, sensor nodes are grouped according to the distance to sink node. Then, each group uses a different frequency band. The proposed scheme not only enables all sensor nodes to maintain the signal-to-noise ratio above a certain required level (Accepted Minimum SNR, AMS), but also reduces overall transmission power consumption. In addition, the dynamic sub-channel allocation is employed in order to improve data transmission rate. Simulations show that proposed MAC protocol has better performance in a delay-tolerant underwater acoustic sensor networks.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.

• Journal of The Korean Society of Grassland and Forage Science
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• v.43 no.1
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• pp.22-27
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• 2023

This experiment was conducted to confirm the possibility of preparing Sorghum×sudangrass hybrid artificial hay using far-infrared rays in Korea. The machine used in this experiment is a drying device based on far-infrared rays, and is designed to control temperature, air flow rate, far-infrared radiation amount, and air flow speed. The Sorghum×sudangrass hybrids harvested in late September were wilted in the field for one day, and a drying test was performed on them. Conditions for drying were performed by selecting a total of 7 conditions, and each condition induced a change in radiation amount in a single condition (42%) and two steps (4 treatments) and three steps (2 treatments). The speed of the air flow in the device was fixed at 60 m/s, and the run time was changed to 30, 60, and 90 minutes. The average dry matter (DM) content was 82.84%. The DM content was 59.94 and 76.91%, respectively, in drying conditions 1 and 3, which were not suitable for hay. In terms of drying rate, it was significantly higher than 80% in the 5, 6 and 7 treatment, and power consumption was slightly high with an average of 5.7 kw/h. As for the feed value according to each drying condition, the crude protein (CP) content increased as the drying time increased, and there was no significant difference between treatments in ADF, NDF, IVDMD and TDN content. In terms of RFV, treatment 1, which is a single condition, was significantly lower than the complex condition. Through the above results, it was determined that the drying conditions 4 and 5 were the most advantageous when considering the drying speed, power consumption, and quality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• International Journal of Automotive Technology
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• v.6 no.3
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• pp.221-227
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• 2005

Aim of this study is to investigate an aerodynamic effect of a drag-reducing device on a heavy-duty truck. The vehicle experiences two different kinds of aerodynamic forces such as drag and uplifting force (or downward force) as it is traveling straight forward at constant speed. The drag force on a vehicle may cause an increase of the rate of fuel consumption and driving instability. The rolling resistance of the vehicle may be increased as result of the negative uplifting or downward force on the vehicle. A device named roof-fairing system has been applied to examine the reduction of aerodynamic drag force on a heavy-duty truck. As for a engineering design information, the drag-reducing system should be studied theoretically and experimentally for the best efficiency of the device. Four different types of roof-fairing model were considered in this study to investigate the aerodynamic effect on a model truck. The drag and downward force generated by vehicle has been obtained from numerical calculation conducted in this study. The forces produced on four fairing models considered in this study has been compared each other to evaluate the best fairing model in terms of aerodynamic performance. The result shows that the roof-fairing mounted truck has bigger negative uplifting or downward force than that of non-mounted truck in all speed ranges, and drag force on roof-fairing mounted truck has smaller than that of non-mounted truck. The drag coefficient $(C_D)$ of the roof-fairing mounted truck (Model-3) is reduced up to $41.3\%$ than that of non-mounted trucks (Model-1). A downward force generated by a roof-fairing mounted on a truck is linearly proportional to the rolling resistance force. Therefore, the negative lifting force on a heavy-duty truck is another important factor in aerodynamic design parameter and should be considered in the design of a drag-reducing device of a tractor-trailer. According to the numerical result obtained from present study, the drag force produced by the model-3 has the smallest of all in all speed ranges and has reasonable downward force. The smaller drag force on model-3 with 2/3h in height may results of smallest thickness of boundary layer generated on the topside of the container and the lowest intensity of turbulent kinetic energy occurs at the rear side of the container.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.6-13
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• 2006

Tin doped indium oxide(ITO) and Al doped zinc oxide(ZnO:Al) films, which are widely used as a transparent conductor in optoelectronic devices, were prepared by using the capacitively coupled DC magnetron sputtering method. ITO and ZnO:Al films with the optimum growth conditions showed each resistivity of $1.67{\times}10^{-3}[{\Omega}-cm],\;2.2{\times}10^{-3}[{\Omega}-cm]$ and transmittance of 89.61[%], 90.88[%] in the wavelength range of the visible spectrum. The two types of 5 inch-PDP cells with ZnO:Al and ITO transparent electrodes were made under the same manufacturing conditions. The PDP cell with ZnO:Al film was optimally operated in the mixing gas rate of Ne(base)-Xe(8[%]), and at gas pressure of 400[Torr]. It also shows the average measured brightness of $836[cd/m^2]$ at voltage range of $200{\sim}300$[V]. Luminous efficiency, one of the key parameter for high brightness and low power consumption, ranges from 1.2 to 1.6[lm/W] with increasing frequency of ac power supplier from 10 to 50[Khz]. The brightness and luminous efficiency are lower than those with ITO electrode by about 10[%]. However, these values are considered to be enough for the normal operation of PDP TV.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.458-465
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• 2020

The purpose of this study is to analyze the effect of policy in Jeju, using a macro-economic forecasting model of Jeju. First, the model's reality explanatory power improved by updating its statistics to 2017 and expanding new policy variables and modules. Also, the industrial structure of the model was further subdivided and extended to be considered simultaneously in the demand side of Keynesian theory. Second, it was determined that the predictive power for the model of this study was better than that of the existing model. However, with some endogenous variables, it was possible to identify implications that should be developed and considered when the model is improved with additional data in the future. Third, when the second airport construction was considered, it was observed that its effect was an increase of 1.25 times for GRDP, 1.2 times for employment, 1.48 times for private consumption, and 2.06 times for investment. Also, the economic growth rate was estimated to be 1.6% point higher than when the second airport was not constructed. Finally, the results of this study are expected to be used for policy decision making of the Jeju Government.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.