• 한국세라믹학회지
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• 제27권2호
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• pp.249-255
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• 1990

High Tc Supperconducting thin films were fabricated by rf magnetron sputtering method. We have successfully controlled the compositions of films by adding sintered CuO pellets on YBa2Cu3O7-x single target. High Tc thin films with large grian size and good crystal habit were obtained by rapid thermal annealing process. The films deposited on SrTiO3(100) single crystal substrate indicated the existence of c-axis prefered orientation confirmed by XRD and SEM analysis. The Tc, zero's of sharp resistive transition for rapid annealed films deposited on polycrystalline YSZ substrate and on SrTiO3(100) single crystal substrate were 79K and 88K, respectively.

• 한국전기전자재료학회논문지
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• 제17권1호
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• pp.7-15
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• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.30-33
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• 2004

Shallow p+-n junctions were formed by low-energy ion implantation and dual-step annealing processes The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth. A new simulator is designed to model boron diffusion in silicon, which is especially useful for analyzing the annealing process subsequent to ion implantation. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using a resonable parameter values, the simulator covers not only the equilibrium diffusion conditions but also the nonequilibrium post-implantation diffusion. Using initial conditions and boundary conditions, coupled diffusion equation is solved successfully. The simulator reproduced experimental data successfully.

• 한국표면공학회지
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• 제28권2호
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• 한국세라믹학회지
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• 제40권12호
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• pp.1189-1196
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• 2003

Sol-gel법으로 강유전성 B $i_{3.25}$L $a_{0.75}$ $Ti_3$ $O_{12}$ (BLT) stock solution을 합성하고 Pt/Ti $O_2$/ $SiO_2$/Si 기판위에 스핀코팅법으로 BLT 박막을 증착하였다. 본 실험에서는 Bi(TMHD)$_3$, La(III)2-Methoxyethoxide, Ti(IV)i-propoxide를 출발물질로 사용하였으며 2-Methoxyethanol을 용매로 사용하였다. 급속열처리(RTA)가 BLT 박막의 결정성장을 촉진시키기 위해 사용되었고, RTA를 실시한 시편과 RTA를 실시하지 않은 시편의 전기적 특성을 비교하였다. RTA를 실시한 후 72$0^{\circ}C$에서 로 열처리 한 BLT 박막의 경우 5V 인가 전압 하에서 2Pr 값은 RTA를 실시하지 않은 경우보다 27% 증가한 20.46$\mu$C/$ extrm{cm}^2$이었다.

• 한국세라믹학회지
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• 제37권5호
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• pp.425-431
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• 2000

Cobalt ferrite thin films on Corming glass substrate were fabricated by a sol-gel method. Cobalt ferrite thin films with the grain size of 20-35 nm and thickness of 50nm were obtained. Rapid thermal annealing (RTA) and Annealing processes were adopted for comparison of characteristics of the films. Coercivity values were changed with thermal condition and magnetization values were increased as a function of soaking time. With prolonged soaking time, however, it was decreased because of the diffusion of cations from the glass substrate. The RTA process in preparation of cobalt ferrite thin film was the effective way to prevent and to form a single spinel phase in reduced soaking time. The film heated at 600$^{\circ}C$ for 30 minutes by RTA had coercivity of 2,600 Oe, saturation magnetization 460 emu/㎤, and Mr$.$$\delta$ of 1.43 memu/$\textrm{cm}^2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.130.2-130.2
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• 2013

Today, chemical vapor deposition (CVD) of hydrocarbon gases has been demonstrated as an attractive method to synthesize large-area graphene layers. However, special care should be taken to precisely control the resulting graphene layers in CVD due to its sensitivity to various process parameters. Therefore, a facile synthesis to grow graphene layers with high controllability will have great advantages for scalable practical applications. In order to simplify and create efficiency in graphene synthesis, the graphene growth by thermal annealing process has been discussed by several groups. However, the study on growth mechanism and the detailed structural and optoelectronic properties in the resulting graphene films have not been reported yet, which will be of particular interest to explore for the practical application of graphene. In this study, we report the growth of few-layer, large-area graphene films using rapid thermal annealing (RTA) without the use of intentional carbon-containing precursor. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2~3 nm) carbon- and oxygen-containing compounds on a nickel surface and high-temperature annealing of the nickel samples results in the formation of few-layer graphene films with high crystallinity. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time and the resulting films have a limited thickness less than 2 nm even for an extended RTA time. The transferred films have a low sheet resistance of ~380 ${\Omega}/sq$, with ~93% optical transparency. This simple and potentially inexpensive method of synthesizing novel 2-dimensional carbon films offers a wide choice of graphene films for various potential applications.

• 한국재료학회지
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• 제10권1호
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• pp.29-33
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• 2000

비정질 WNx 박막이 반응성 스퍼터링법으로 제조되었다. 비정질 형성을 위한 질소의 농도범위는 10~40at%이었다. 비정질 W(sub)67N(sub)33 박막은 1273K에서 1분 동안 급속 열처리되어 저항이 낮은 등축정의 $\alpha$-텅스텐 상과 과잉의 질소로 변태되었다. 이러한 박막의 저항은 순수한 텅스텐 박막과 유사하였다. $\alpha$-텅스텐 상으로부터 방출된 과잉의 질소는 $\alpha$-텅스텐/다결정 실리콘의 계면에 편석되었다. 편석된 질소는 Si$_3$N$_4$나노 결정으로 균일한 확산 장벽층을 형성시켰고, 저항이 높은 텅스텐 실리사이드의 반응을 억제하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2004년도 춘계학술대회
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• pp.1370-1375
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• 2004

This article investigates the heat transfer characteristics in a RTA system for LCD manufacturing and suggests a way to evaluate the quality of a poly-Si film from the thin film optics analysis. The transient and one-dimensional conductive/radiative heat transfer equation considering wave interference effect is solved to predict surface temperatures of thin films. In dealing with radiative heat transfer, a one-dimensional two-flux method is used and the ray tracing method is also utilized to account for the wave interference effects. It is assumed that each interface is assumed diffusive but the spectral radiative properties are included. It is found that the selective heating region exists for various wavelengths and consequently may contribute to heat the poly-Si film. Using the formalism of the characteristic transmission matrix, the lumped structure reflectance, transmittance, and absorptance are calculated and they are compared with experimental data of the poly-Si film during the SPC process via the FE-RTA (Field-Enhanced RTA) technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.