• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.6-11
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• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.290-293
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• 2003

Ohmic contact characteristics of Al ion implanted n-type SiC wafer were investigated. Al ions implanted with high dose to obtain the final concentration of $5{\times}10^{19}/cm^3$, then annealed at high temperature. Firstly, B ion ion implanted p-well region were formed which is needed for fabrication of SiC devices such as DIMOSFET and un diode. Secondly, Al implanted high dose region for ohmic contact were formed. After ion implantation, the samples were annealed at high temperature up to $1600^{\circ}C\;and\;1700^{\circ}C$ for 30 min in order to activate the implanted ions electrically. Both the inear TLM and circular TLM method were used for characterization. Ni/Ti metal layer was used for contact metal which is widely used in fabrication of ohmic contacts for n-type SiC. The metal layer was deposited by using RF sputtering and rapid thermal annealed at $950^{\circ}C$ for 90sec. Good ohmic contact characteristics could be obtained regardless of measuring methods. The measured specific contact resistivity for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$ were $1.8{\times}10^{-3}{\Omega}cm^2$, $5.6{\times}10^{-5}{\Omega}cm^2$, respectively. Using the same metal and same process of the ohmic contacts in n-type SiC, it is found possible to make a good ohmic contacts to p-type SiC. It is very helpful for fabricating a integrated SiC devices. In addition, we obtained that the ratio of the electrically activated ions to the implanted Al ions were 10% and 60% for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$, respectively.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.149-154
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• 2005

궁극적으로 게이트를 저저항 복합 실리사이드로 대체하는 가능성을 확인하기 위해 70 nm 두께의 폴리실리콘 위에 각 20nm의 Ni, Co를 열증착기로 적층순서를 달리하여 poly/Ni/Co, poly/Co/Ni구조를 만들었다. 쾌속열처리기를 이용하여 실리사이드화 열처리를 40초간 $700{\~}1100^{\circ}C$ 범위에서 실시하였다. 복합 실리사이드의 온도별 전기저항변화, 두께변화, 표면조도변화를 각각 사점전기저항측정기와 광발산주사전자현미경, 주사탐침현미경으로 확인하였다. 적층순서와 관계없이 폴리실리콘으로부터 제조된 복합실리사이드는 $800^{\circ}C$ 이상부터 급격한 고저항을 보이고, 두께도 급격히 얇아졌다. 두께의 감소는 기존의 단결정에서는 없던 현상으로 폴리실리콘의 두께가 한정된 경우 금속성분의 inversion 현상이 커서 폴리실리콘이 오히려 실리사이드 상부에 위치하여 제거되기 때문이라고 생각되었고 $1000^{\circ}C$ 이상에서는 실리사이드가 형성되지 못하였다. 이러한 결과는 나노급 두께의 게이트를 저저항 실리사이드로 만 들기 위해서는 inversion과 두께감소를 고려하여야 함을 의미하였다.

• Current Photovoltaic Research
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• 제3권1호
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• pp.32-38
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• 2015

CIGS solar cell consisted of various films. In this research, we investigated electrode materials in $Cu(In,Ga)Se_2$ (CIGS) cells, including Al-doped ZnO (ZnO:Al), intrinsic ZnO (i-ZnO), and Al films. The sputtered ZnO:Al film with a sputtering power at 200W showed the lowest series resistance and highest cell efficiency. The electrical resistivity of the 200-W sputtered ZnO:Al film was $5.2{\times}10^{-4}{\Omega}{\cdot}cm$ by the rapid thermal annealing at $200^{\circ}C$ for 1 min. The electrical resistivity of i-ZnO was not measurable due to its high resistance. But the optical transmittance was highest with less oxygen supply and high efficiency cell was achieved with $O_2/(Ar+O_2)$ ratio was 1% due to the increase of short-circuit current. No significant change in the cell performance by inserting a Ni layer between Al and ZnO:Al films was observed.

• 한국재료학회지
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• 제8권4호
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• pp.359-361
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• 1998

$SiH_{4}$를 반응물질로 사용하여 electron cyclotron resonance plasma enhanced chemical vapor deposition(ECR-PECVD)로 실리콘 기판위에 증착한 수소화 비정질 실리콘(a-Si:H)으로부터 가시 photoluminescence(PL) 가 관찰되었다. a-si:H/Si로 부터의 PL은 다공질실리콘으로부터의 PL과 유사하였다. 급속열처리에 의해 $500^{\circ}C$에서 2분간 산소분위기에서 어닐링된 시편의 수소함량은 1~2%로 줄어들었고 시편은 가시 PL을 보여주지 않았는데 이는 a-Si:H의 PL과정에서 수소가 중요한 역할을 한다는 것을 뜻한다. 증착된 a-Si:H의 두께가 증가함에 따라 PL의 세기는 감소하였다. $SiH_{4}$를 사용하여 ECR-PECVD에 의해 Si상에 증착된 a-Si:H로부터의 가시 PL은 Si과 증착된 a-Si:H막 사이에 증착이 이루어지는 동안에 형성된 수소화실리콘으로부터 나오는 것으로 추론된다.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.16-22
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• 2002

본 논문에서는 선비정질화 이온주입과 BPSG(boro-phosphosilicate glass)를 위한 FA(furnace anneal) 공정이 적용된 양질의 p/sup +/-n 박막 접합을 형성하는 공정 조건을 제시하였다. 단결정 실리콘 기판을 As과 Ge 이온으로 45keV와 3×10/sup 14/cm/sup -2/로 주입하여 선비정질화 하였으며, p형 이온으로는 BF₂ 이온을 20keV, 2×10/sup 15/cm/sup -2/로 주입하였다. 고온 열처리는 furnace와 급속 열처기로 수행하였으며, 급속 열처리 온도는 950∼1050℃이며 FA는 BPSG 공정을 위해 850℃/4O분간 수행하였다. 박막 접합의 특성을 고려하기 위해 접합깊이, 면저항 및 다이오드 누설 전류를 측정 ·분석하였다. Ge 이온으로 선비정질화 하였을 경우 As 이온보다 대부분의 접합 특성에서 우수한 결과를 나타내었다. Ge으로 선비정질화하고 1000℃의 RTA를 수행한 경우에 가장 양호한 특성을 나타내었으며, FA를 포함한 경우에는 RTA 1050℃+FA의 열처리 조건에서 Ge 이온으로 선비정질화 했을 때 면저항과 접합깊이의 곱 및 누설 전류에서 양호한 특성을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.195-200
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• 2007

최소선폭 $0.1{\mu}m$ 이하의 살리사이드 공정을 상정하여 $10nm-Ni_{0.5}Co_{0.5}/70\;nm-Poly-Si/200\;nm-SiO_2$ 구조로부터 쾌속 열처리를 이용해서 실리사이드 온도를 $600{\sim}1100^{\circ}C$까지 변화시키면서 복합실리사이드를 제조하고 이들의 면저항의 변화와 미세구조의 변화를 면저항 측정기와 TEM 수직단면, 오제이 두께 분석으로 확인하였다. 기존의 동일한 공정으로 제조된 니켈실리사이드에 비해 제안된 니켈 코발트 복합실리사이드는 $900^{\circ}C$까지 저저항을 유지시킬 수 있는 장점이 있었고 20nm 두께의 균일한 실리사이드 층을 폴리실리콘 상부에 형성시킬 수 있었다. 고온 처리시에는 복합실리사이드와 실리콘의 전기적으로 상분리되는 혼합현상으로 고저항 특성이 나타나는 문제를 확인하였다. 제안된 NiCo 합금 박막을 70nm 높이의 폴리실리콘 게이트를 가진 디바이스에 $900^{\circ}C$이하의 실리사이드화 온도에서 효과적으로 산리사이드 공정의 적용이 기대되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

• 한국진공학회지
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• 제20권5호
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• pp.339-344
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• 2011

C-plane 사파이어 기판 위에 펄스 레이저 증착법으로 증착시킨 n-type ZnO 박막에 대한 Ti/Au 금속의 Ohmic 접합특성을 TLM (transfer length method) 패턴 전극을 통하여 연구하였다. 여기서, Ti와 Au 금속박막은 전자빔 증착기와 열 증착기로 각각 35 nm와 90 nm 두께로 증착하였으며, TLM패턴은 광 리소그래피 법으로 면적이 $100{\times}100{\mu}m^2$인 전극패턴을 6~61 ${\mu}m$ 간격으로 형성하였다. Ti/Au 금속박막과 ZnO 반도체 사이의 전기적인 성질을 개선하고 응력과 계면 결함을 감소시키기 위해, 산소 가스 분위기로 $100{\sim}500^{\circ}C$ 온도에서 각각 1분간 급속열처리를 하였다. $300^{\circ}C$의 온도에서 열처리한 시료에서 $1.1{\times}10^{-4}{\Omega}{\cdot}cm^2$의 가장 낮은 비저항 값을 보였는데, 이것은 열처리 동안 티타늄 산화막 형성과정에서 ZnO 박막 표면 근처에 산소빈자리가 형성됨으로써 나타나는 전자농도의 증가가 주된 원인으로 고려되었다.