• Title/Summary/Keyword: Rapid Thermal Processing (RTP)

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Estimation of Temperature Distribution on Wafer Surface in Rapid Thermal Processing Systems (고속 열처리공정 시스템에서의 웨이퍼 상의 온도분포 추정)

  • Yi, Seok-Joo;Sim, Young-Tae;Koh, Taek-Beom;Woo, Kwang-Bang
    • Journal of Institute of Control, Robotics and Systems
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    • v.5 no.4
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    • pp.481-488
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    • 1999
  • A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

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Robust controller design for RTP system using structured uncertainty approach (구조적 불확실성 접근을 이용한 RTP 시스템의 견실제어기 설계)

  • Lee, Sang-Kyung;Kim, Jong-Hae;Kim, Hae-Kun;Park, Hong-Bae
    • Journal of Institute of Control, Robotics and Systems
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    • v.5 no.6
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    • pp.667-675
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    • 1999
  • In this paper, we propose a robust controller design of RTP(Rapid Thermal Processing) system using structured uncertainty approach. Using the weighted mixed sensitivity function, we solve the robust stability problem against disturbance and temperature variation, and design a $\mu$ controller using curve fitting method against structured uncertainty. Also the reduction method should be requried because of the difficulty of implementaion with the obtained high order controller. We dal with robust stability and performance of RTP system by the design of $\mu$ controller for original model and Schur balanced reduced model. Finally the simulation results are proposed to show the validity of the proposed method.

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Design and Fabrication of Power Controller for Temperature Control on Semiconductor Thermal Processing (반도체 열처리 공정을 위한 온도 조절기용 전력 제어장치의 설계 및 제작)

  • 주동만;민경일;황재효
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.3 no.4
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    • pp.257-262
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    • 2002
  • A design method of a power controller for controlling the temperature adopted in RTP (rapid thermal processing) which uses the phase control method is presented. The power controller is fabricated by using the design method presented in this paper and is tested. As the results, the range of average voltage from the variable output is 0∼198.06 V and the control resolution is 48.356 mV (12 bit) at the range of the input signal (0∼10 V).

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Characteristics of Contact resistivity on RTP annealing temperature and time after Plasma ion implant (플라즈마 이온주입 후 RTP 열처리 온도와 시간에 따른 접촉저항 특성)

  • Choi, Jang-Hun;Do, Seung-Woo;Lee, Yong-Hyun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.5-6
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    • 2009
  • In this paper, plasma ion implant is performed with $PH_3$ gas diluted by helium gas on P-type Si wafer (100). Spike Rapid Thermal Processing(RTP) annealing performed for 30~60 sec from $800\;^{\circ}C$ to $1000\;^{\circ}C$ in $N_2+O_2$ ambient. Crystalline defect is analyzed by Transmission Electron Microscope(TEM) and Double crystal X-ray Diffraction(DXRD). Contact resistivity($\rho c$), contact resistance(Rc) and sheet resistance(Rs) are analyzed by measuring Transfer Length Method(TLM) using 4155C analysis. As annealing temperature increase, Rs decrease and ${\rho}c$ and Rc increase at temperature higher than $850\;^{\circ}C$. We achieve low Rs, ${\rho}c$ and Rc with Plasma ion implant and spike RTP.

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Influence of the Optimized Process in Rapid Thermal Processing on Solar Cells (RTP Furnace에서 공정과정이 태양전지에 미치는 영향)

  • Lee, Ji-Youn;Lee, Soo-Hong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.169-172
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    • 2004
  • The effect of the process parameters on the stable lifetime in rapid thermal firing(RTF) was investigated in order to optimize the process for the Cz-silicon. The process temperature was varied between $700^{\circ}C\;and\;950^{\circ}C$ while the process time was chosen 1 s and 10 s. At below $850^{\circ}C$ the stable lifetime for 10 s is higher than that for 1 s and increases with increasing by the process temperature. However, at over $850^{\circ}C$ the improved stable lifetime is not dependent on the process time and temperature. On the other hand, two high temperature processes in solar cell fabrics are combined with the optimized process and the non-optimized process. The last process determines the stable lifetime. Also, the degraded stable lifetime could be increased by processing in optimized process. The decreased lifetime can increase using the optimized oxidation process, which is a final process in solar cells. Finally, the optimized and non-optimized processes are applied solar cells.

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DC Sputtering Process of 2-Dimensional Tungsten Disulfide Thin Films on Soda-Lime Glass Substrates (DC 스퍼터링을 이용한 소다라임 유리 기판상에 2차원 황화텅스텐 박막 형성 공정)

  • Ma, Sang Min;Kwon, Sang Jik;Cho, Eou Sik
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.3
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    • pp.31-35
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    • 2018
  • Tungsten disulfide($WS_2$) thin films were directly deposited by direct-current(DC) sputtering and annealed by rapid thermal processing(RTP) to materialize two-dimensional p-type transition metal dichalcogenide (TMDC) thin films on soda-lime glass substrates without any complicated exfoliation/transfer process. $WS_2$ thin films deposited at various DC sputtering powers from 80 W to 160W were annealed at different temperatures from $400^{\circ}C$ to $550^{\circ}C$ considering the melting temperature of soda-lime glass. The optical microscope results showed the stable surface morphologies of the $WS_2$ thin films without any defects. The X-ray photoelectron spectroscopy (XPS) results and the Hall measurement results showed stable binding energies of W and S and high carrier mobilities of $WS_2$ thin films.

Implementation of process and surface inspection system for semiconductor wafer stress measurement (반도체 웨이퍼의 스트레스 측정을 위한 공정 및 표면 검사시스템 구현)

  • Cho, Tae-Ik;Oh, Do-Chang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.11-16
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    • 2008
  • In this paper, firstly we made of the rapid thermal processor equipment with the specifically useful structure to measure wafer stress. Secondly we made of the laser interferometry to inspect the wafer surface curvature based on the large deformation theory. And then the wafer surface fringe image was obtained by experiment, and the full field stress distribution of wafer surface comes into view by signal processing with thining and pitch mapping. After wafer was ground by 1mm and polished from the back side to get easily deformation, and it was heated by three to four times thermal treatments at about 1000 degree temperature. Finally the severe deformation between wafer before and after the heat treatment was shown.

Cost-effective surface passication layers by RTP and PECVD (RTP 와 PECVD을 이용한 저가의 표면 passivation 막들의 특성연구)

  • Lee, Ji-Youn;Lee, Soo-Hong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.05a
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    • pp.142-145
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    • 2004
  • In this work, we have investigated the application of rapid thermal processing (RTP) and plasma enhanced chemical vapour deposition (PECVD) for surface passivation. Rapid thermal oxidation (RTO) has sufficiently low surface recombination velocities (SRV) $S_{eff}$ in spite of a thin oxides and short process time. The effective lifetime is increasing with an increase of the oxide thickness. In the same oxide thickness, The effective lifetime is independent on the process temperature and time. $S_{eff,max}$ is exponentially decreased with increasing oxide thickness. $S_{eff,max}$ can be reduced to 200 cm/s with only 10 nm oxide thickness. On the other hand, three different types of SiN are reviewed. SiN1 layer has a thickness of about 72 nm and a refractive index of 2.8. Also, The SiN1 has a high passivation quality. The effective lifetime and SRV of 1 $\Omega$ cm Float zone (FZ) silicon deposited with SiN1 is about 800 s and under 10 cm/s, respectively. The SiN2 is optimized for the use as an antireflection layer since a refractive index of 2.3. The SiN3 is almost amorphous silicon caused by less contents of N2 from total process. The effective lifetime on the FZ 1 ${\Omega}cm$ is over 1000 ${\mu}s$.

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Nonlinear Optimal Control of an Input-Constrained and Enclosed Thermal Processing System

  • Gwak, Kwan-Woong;Masada, Glenn Y.
    • International Journal of Control, Automation, and Systems
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    • v.6 no.2
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    • pp.160-170
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    • 2008
  • Temperature control of an enclosed thermal system which has many applications including Rapid Thermal Processing (RTP) of semiconductor wafers showed an input-constraint violation for nonlinear controllers due to inherent strong coupling between the elements [1]. In this paper, a constrained nonlinear optimal control design is developed, which accommodates input constraints using the linear algebraic equivalence of the nonlinear controllers, for the temperature control of an enclosed thermal process. First, it will be shown that design of nonlinear controllers is equivalent to solving a set of linear algebraic equations-the linear algebraic equivalence of nonlinear controllers (LAENC). Then an input-constrained nonlinear optimal controller is designed based on that LAENC using the constrained linear least squares method. Through numerical simulations, it is demonstrated that the proposed controller achieves the equivalent performances to the classical nonlinear controllers with less total energy consumption. Moreover, it generates the practical control solution, in other words, control solutions do not violate the input-constraints.

Material and Electrical Characteristics of Oxynitride Gate Dielectrics prepared in $N_2$O ambient by Rapid Thermal Process (RTP로 $N_2$O 분위기에서 제조한 Oxynitride Gate 절연체의 물질적 전기적 특성)

  • Park, Jin-Seong;Lee, Woo-Sung;Shim, Tea-Earn;Lee, Jong-Gil
    • Korean Journal of Materials Research
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    • v.2 no.4
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    • pp.285-292
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    • 1992
  • Ultrathin(8nm) oxynitride (SiOxNy) film have been formed on Si(100) by rapid thermal processing(RTP) in $O_2$and $N_2$O as reactants. Compared with conventional furnace $O_2$ oxide, the oxynitride dielectrics shows better characteristics of I-V and TDDB, and less flat-band voltage shift. The oxynitride has a behavior of Fowler-Nordheim tunneling in the region of V 〉${\varphi}_0$ simialr to pure Si$O_2$oxide. The relative dielectric constant of oxynitride is higher than that of conventional pure oxide. Excellent diffusion harrier property to dopant(B$F_2$) is also observed. Nitrogen depth profiles by SIMS, AES, and XPS show nitrogen pile - up at Si$O_2$/Si interface, which can explain the improved properties of oxynitride dielectrics.

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