• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.481-482
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• 2022

본 논문은 MOSFET 트랜지스터로 구성된 monolithic 3D 인버터의 구조에서 하부 MOSFET 게이트 전압의 변화에 따라서 상부 MOSFET 트랜지스터의 random dopant fluctuation(RDF) 영향을 3차원 소자 시뮬레이션을 통하여 조사하였다. RDF 영향 조사를 위한 표본화는 kinetic monte carlo 방식을 통하여 진행하였으며, RDF 영향이 트랜지스터의 임계전압 변동에 영향을 주는 것을 확인하였고, 상부 트랜지스터와 하부 트랜지스터 사이에 전기적 커플링을 조사하였다.

• 전자공학회논문지
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• 제49권12호
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• pp.179-183
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• 2012

3차원 시뮬레이션을 이용하여 터널링 전계효과 트랜지스터(TFET)의 불순물 분포 변동(RDF) 효과에 대해 살펴보았다. TFET의 RDF 효과는 매우 낮은 바디 도핑 농도 때문에 많이 논의되지 않았다. 하지만 본 논문에서는 임의로 생성되고 분포되는 소스 불순물이 TFET의 문턱전압 ($V_{th}$)과 드레인 유기 전류 증가 (DICE), 문턱전압이하 기울기 (SS)의 변화를 증가시킴을 발견하였다. 또한, TFET의 RDF 효과를 감소시킬 수 있는 몇 가지 방법을 제시하였다.

• 전기전자학회논문지
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• 제21권1호
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• pp.96-99
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• 2017

본 연구에서는 금속-산화막-반도체 전계효과 트랜지스터의 불순물 분포변동 효과에 미치는 halo 및 LDD 이온주입 공정의 영향을 3차원 소자 시뮬레이션을 통하여 확인하였다. 정확한 시뮬레이션 계산을 위해 kinetic monte carlo 모델을 적용하여 불순물 입자와 결함 낱낱의 거동을 계산하는 원자단위 시뮬레이션을 수행하였다. 문턱전압 및 on-current의 산포를 통해 확인한 결과 halo 이온주입 공정이 LDD 이온주입 공정보다 문턱전압 산포의 경우 약 6.45배 그리고 on-current 산포의 경우 2.46배 더 큰 영향을 미치는 특성을 확인하였다. 그리고 문턱전압과 on-current 산포를 히스토그램으로 나타내어 그 산포를 정규분포로 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.365-375
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• 2014

This paper proposes an abnormal V-shaped-error-free non-blind deconvolution technique featuring an adaptively segmented forward-problem based iterative deconvolution (ASDCN) process. Unlike the algebraic based inverse operations, this eliminates any operations of differential and division by zero to successfully circumvent the issue on the abnormal V-shaped error. This effectiveness has been demonstrated for the first time with applying to a real analysis for the effects of the Random Telegraph Noise (RTN) and/or Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. It has been shown that the proposed ASDCN technique can reduce its relative errors of RTN deconvolution by $10^{13}$ to $10^{15}$ fold, which are good enough for avoiding the abnormal ringing errors in the RTN deconvolution process. This enables to suppress the cdf error of the convolution of the RTN with the RDF (i.e., fail-bit-count error) to $1/10^{10}$ error for the conventional algorithm.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.216-225
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• 2013

This paper discusses the issues regarding an abnormal V-shaped error confronting algebraic-based deconvolution process. Deconvolution was applied to an analysis of the effects of the Random Telegraph Noise (RTN) and Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. This paper proposes a technique to suppress the problematic phenomena in the algebraic-based RDF/RTN deconvolution process. The proposed technique can reduce its relative errors by $10^{10}$ to $10^{16}$ fold, which is a sufficient reduction for avoiding the abnormal ringing errors in the RTN deconvolution process. The proposed algebraic-based analyses allowed the following: (1) detection of the truncating point of the TD-MV distributions by the screening test, and (2) predicting the MV-shift-amount by the assisted circuit schemes needed to avoid the out of specs after shipment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.