• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.130-135
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• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.274-277
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• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.208-209
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• 2008

Ni/Ti/Al multilayer system was tested for low-resistance ohmic contact formation to Al-implanted p-type 4H-SiC. Compared with conventional process using Ni, Ni/Ti/Al contact shows perfect ohmic behavior, and possesses much lower contact resistance of about $2.5\times10^{-4}\Omega{\cdot}cm^2$ after $930^{\circ}C$ RTA, which is about 2 orders of magnitude smaller than that of Ni contact. Contact resistance gradually increased as the RTA temperature was lowered in the range of 840 ~ $930^{\circ}C$, and about $3.4\times10^{-4}\Omega{\cdot}cm^2$ was obtained at the lowest RTA temperature of $840^{\circ}C$. Therefore, it was shown that RTA temperature for ohmic contact formation can be lowered to at least $840^{\circ}C$ without significant compromise of contact resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.341-344
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• 1999

The effects of post annealing treatments of ferroelectrlclty in PZT(P $b_{1.05}$(Z $r_{0.52}$, $Ti_{0.48}$) $O_3$ thin film deposited on Pt/ $SiO_2$/Si substrate by RF-Magnetron sputtering methode was Investigated. Analyses by RTA(Rapid Thermal Annealing) treatments reveled that the crystallization process strongly depend on the healing temperature. The Perovskite structure with strong PZT (101) plan was obtained by RTA treatments at 75$0^{\circ}C$ With increasing RTA temperature of PZI thin films, the coercive field and remanent Polarization decreased, while saturation polarization( $P_{r}$) was decreased. P-E curves of Pt/PZT/Pt capacitor structures demonstrate typical hysteresiss loops. The measure values of $P_{r}$,. $E_{c}$ and dielectric constants by post annealed at 75$0^{\circ}C$ were 38 $\mu$C/$\textrm{cm}^2$ 35KV/cm and 974, respectively. Switching polarization versus fatigue characteristic showed 12% degradation up to 10$^{7}$ cycles.s.s.s.s.s.s.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1370-1375
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• 2004

This article investigates the heat transfer characteristics in a RTA system for LCD manufacturing and suggests a way to evaluate the quality of a poly-Si film from the thin film optics analysis. The transient and one-dimensional conductive/radiative heat transfer equation considering wave interference effect is solved to predict surface temperatures of thin films. In dealing with radiative heat transfer, a one-dimensional two-flux method is used and the ray tracing method is also utilized to account for the wave interference effects. It is assumed that each interface is assumed diffusive but the spectral radiative properties are included. It is found that the selective heating region exists for various wavelengths and consequently may contribute to heat the poly-Si film. Using the formalism of the characteristic transmission matrix, the lumped structure reflectance, transmittance, and absorptance are calculated and they are compared with experimental data of the poly-Si film during the SPC process via the FE-RTA (Field-Enhanced RTA) technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.500-501
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• 2005

Aluminum doped zinc oxide films (ZnO:Al) were deposited on glass substrate by DC magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The effects of substrate bias on the electrical properties and film structure were studied. Films deposited with positive bias have been annealed at $600^{\circ}C$ using rapid thermal anneal (RTA) process. The effects of RTA on the evolution of film microstructure are to be also studied using X-ray diffraction, transmission electron microscopy, and atomic force microscopy. Positive bias sputtering may induce lattice defects caused by electron bombardments during deposition. The as-deposited film microstructure evolves from the film with high defect density to more stable film condition. The electrical properties of the films after RTA process were also studied and the results were correlated with the evolution of film microstructures.

• Journal of the Optical Society of Korea
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• v.20 no.1
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• pp.130-134
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• 2016

The influence of Au/Ni-based contact formed on a lightly-doped (7.3×1017cm−3, Zn-doped) InGaAsP layer for electrical compensation of surface plasmon polariton (SPP) propagation under various rapid thermal annealing (RTA) conditions has been studied. The active control of SPP propagation is realized by electrically pumping the InGaAsP multiple quantum wells (MQWs) beneath the metal planar waveguide. The metal planar film acts as the electric contact layer and SPP waveguide, simultaneously. The RTA process can lower the metal-semiconductor electric contact resistance. Nevertheless, it inevitably increases the contact interface morphological roughness, which is detrimental to SPP propagation. Based on this dilemma, in this work we focus on studying the influence of RTA conditions on electrical control of SPPs. The experimental results indicate that there is obvious degradation of electrical pumping compensation for SPP propagation loss in the devices annealed at 400℃ compared to those with no annealing treatment. With increasing annealing duration time, more significant degradation of the active performance is observed even under sufficient current injection. When the annealing temperature is set at 400℃ and the duration time approaches 60s, the SPP propagation is nearly no longer supported as the waveguide surface morphology is severely changed. It seems that eutectic mixture stemming from the RTA process significantly increases the metal film roughness and interferes with the SPP signal propagation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Korean Journal of Materials Research
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• v.27 no.2
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• pp.94-99
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• 2017

Dinickel-silicide $(Ni_2Si)/glass$ was employed as a counter electrode for a dye-sensitized solar cell (DSSC) device. $Ni_2Si$ was formed by rapid thermal annealing (RTA) at $700^{\circ}C$ for 15 seconds of a 50 nm-Ni/50 nm-Si/glass structure. For comparison, $Ni_2Si$ on quartz was also prepared through conventional electric furnace annealing (CEA) at $800^{\circ}C$ for 30 minutes. XRD, XPS, and EDS line scanning of TEM were used to confirm the formation of $Ni_2Si$. TEM and CV were employed to confirm the microstructure and catalytic activity. Photovoltaic properties were examined using a solar simulator and potentiostat. XRD, XPS, and EDS line scanning results showed that both CEA and RTA successfully led to tne formation of nano $thick-Ni_2Si$ phase. The catalytic activity of $CEA-Ni_2Si$ and $RTA-Ni_2Si$ with respect to Pt were 68 % and 56 %. Energy conversion efficiencies (ECEs) of DSSCs with $CEA-Ni_2Si$ and $RTA-Ni_2Si$catalysts were 3.66 % and 3.16 %, respectively. Our results imply that nano-thick $Ni_2Si$ may be used to replace Pt as a reduction catalytic layer for a DSSCs. Moreover, we show that nano-thick $Ni_2Si$ can be made available on a low-cost glass substrate via the RTA process.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.458.2-458.2
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• 2014

We have demonstrated that simple brush-painted Ti-doped $In_2O_3$(TIO) films can be used as a cost effective transparent anodes for organic solar cells (OSCs). We examined the RTA effects on the electrical, optical, and structural properties of the brush painted TIO electrodes. By the direct brushing of TIO nanoparticle ink and rapid thermal annealing (RTA), we can simply obtain TIO electrodes with a low sheet resistance of 28.25 Ohm/square and a high optical transmittance of 85.48% under atmospheric ambient conditions. Furthermore, improvements in the connectivity of the TIO nano-particles in the top region during the RTA process play an important role in reducing the resistivity of the brush-painted TIO anode. In particular, the brush painted TIO films showed a much higher mobility ($33.4cm^2/V-s$) than that of previously reported solution-process transparent oxide films ($1{\sim}5cm^2/V-s$) due to the effects of the Ti dopant with higher Lewis acid strength (3.06) and the reduced contact resistance of TIO nanoparticles. The OSCs fabricated on the brush-painted TIO films exhibited cell-performance with an open circuit voltage (Voc) of 0.61 V, shot circuit current (Jsc) of $7.90mA/cm^2$, fill factor (FF) of 61%, and power conversion efficiency (PCE) of 2.94%. This indicates that brush-painted TIO film is a promising cost-effective transparent electrode for printing-based OSCs with its simple process and high performance.