• 제목/요약/키워드: ROM data

검색결과 374건 처리시간 0.026초

스핀코터의 진동 평가를 통한 이상 검출 시스템 개발 (Fault Detection System Development for a Spin Coater Through Vibration Assessment)

  • 문준희;이봉구
    • 한국정밀공학회지
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    • 제26권11호
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    • pp.47-54
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    • 2009
  • Spin coaters are the essential instruments in micro-fabrication processes, which apply uniform thin films to flat substrates. In this research, a spin coater diagnosis system is developed to detect the abnormal operation of TFT-LCD process in real time. To facilitate the real-time data acquisition and analysis, the circular-buffered continuous data transfer and the short-time Fourier transform are applied to the fault diagnosis system. To determine whether the system condition is normal or not, a steady-state detection algorithm and a frequency spectrum comparison algorithm using confidence interval are newly devised. Since abnormal condition of a spin coater is rarely encountered, algorithm is tested on a CD-ROM drive and the developed program is verified by a function generator. Actual threshold values for the fault detection are tuned in a spin coater in process.

차세대 팩스 영상처리를 위한 1-Chip Application-Specific DSP 기법 (Development of a 1-Chip Application-Specific DSP for the Next Generation FAX Image Processing)

  • 김재호;강구수;김서규;이진우;이방원;김윤수;조석팔;하성한
    • 전자공학회논문지B
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    • 제31B권4호
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    • pp.30-39
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    • 1994
  • A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

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MCSVM을 이용한 반도체 공정데이터의 과소 추출 기법 (Under Sampling for Imbalanced Data using Minor Class based SVM (MCSVM) in Semiconductor Process)

  • 박새롬;김준석;박정술;박승환;백준걸
    • 대한산업공학회지
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    • 제40권4호
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    • pp.404-414
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    • 2014
  • Yield prediction is important to manage semiconductor quality. Many researches with machine learning algorithms such as SVM (support vector machine) are conducted to predict yield precisely. However, yield prediction using SVM is hard because extremely imbalanced and big data are generated by final test procedure in semiconductor manufacturing process. Using SVM algorithm with imbalanced data sometimes cause unnecessary support vectors from major class because of unselected support vectors from minor class. So, decision boundary at target class can be overwhelmed by effect of observations in major class. For this reason, we propose a under-sampling method with minor class based SVM (MCSVM) which overcomes the limitations of ordinary SVM algorithm. MCSVM constructs the model that fixes some of data from minor class as support vectors, and they can be good samples representing the nature of target class. Several experimental studies with using the data sets from UCI and real manufacturing process represent that our proposed method performs better than existing sampling methods.

네트웍을 통한 음향 전송 장치 구현 (Implementation of a audio transmission device over the network)

  • 송성근;박성모
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.633-634
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    • 2008
  • In this paper, we describe implementation of a network Speaker for easily read streaming audio data from the network. The Network Speaker uses MAXIM company's DS80C400 for network control and MAX542 for audio data play. The DS80C400 network microcontroller offers TCP IPv4/6 network stack with the TINI-OS provided in ROM. The TINI-OS is adopted as an embedded operating system. Application programs are implemented by using JAVA language.

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TCP/IP프로토콜 스택 프로세서 IP의 VLSI설계 (VLSI Design of Processor IP for TCP/IP Protocol Stack)

  • 최병윤;박성일;하창수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.927-930
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    • 2003
  • In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

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TMS320C6201을 이용한 2.4 kbps STC 음성 부호화기의 실시간 구현 (Implementation of 2.4 kbps STC Speech Codec on the TMS320C6201)

  • 유승형;이승원;배건성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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    • pp.167-170
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    • 2002
  • In this paper, we implement a 2.4 kbps STC speech codec using the TMS320C6201 DSP The main job for this work is twofold: one is to convert floating-point operation in the codec into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real time with memory size as small as possible. The implemented decoder uses 54.8 kbyte of program memory, 29.7 kbyte of data ROM and 55.2 kbyte of data RAM, respectively. It also uses about 45% of maximum computation capacity of TMS320C6201.

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MEPG-2 AAC 디코더를 위한 고속 IMDCT 알고리즘 (A fast IMDCT algorithm for MPEG-2 AAC decoder)

  • 지화준;김태훈;조군식;박주성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2007년도 하계종합학술대회 논문집
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    • pp.261-262
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    • 2007
  • This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT(Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The IFFT used in $2^N$-point IMDCT employ the bit-reverse data arrangement of inputs and N/4-IFFT to reduce the calculation cycles. We devised a new data arrangement algorithm of IFFT input and N/$4^{n+1}$-IFFT and can reduce multiplication cycles, addition cycles, and ROM size.

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Emergency Monitoring System Based on a Newly-Developed Fall Detection Algorithm

  • Yi, Yun Jae;Yu, Yun Seop
    • Journal of information and communication convergence engineering
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    • 제11권3호
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    • pp.199-206
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    • 2013
  • An emergency monitoring system for the elderly, which uses acceleration data measured with an accelerometer, angular velocity data measured with a gyroscope, and heart rate measured with an electrocardiogram, is proposed. The proposed fall detection algorithm uses multiple parameter combinations in which all parameters, calculated using tri-axial accelerations and bi-axial angular velocities, are above a certain threshold within a time period. Further, we propose an emergency detection algorithm that monitors the movements of the fallen elderly person, after a fall is detected. The results show that the proposed algorithms can distinguish various types of falls from activities of daily living with 100% sensitivity and 98.75% specificity. In addition, when falls are detected, the emergency detection rate is 100%. This suggests that the presented fall and emergency detection method provides an effective automatic fall detection and emergency alarm system. The proposed algorithms are simple enough to be implemented into an embedded system such as 8051-based microcontroller with 128 kbyte ROM.

원칩마이컴을 이용한 실시간 데이터 저장을 위한 알고리즘 설계 (The Design of Algorithm for Saving the Real-time Data Using Microprocessor)

  • 신사현;김기범;조금배;백형래;서진연;최낙일
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 전력전자학술대회 논문집
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    • pp.657-661
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    • 2001
  • In This paper describes on the development of detecting power using Microprocessor. The detecting power system is composed of main controller system and analyzing software. Re system detected voltage, current, temperature, leakage current md its saved in ROM. This system applies the 'AT89C52' to CPU and 'AM29F040B' used a memory to sue the data.

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멀티미디어 홈 네트워크 실현을 위한 WLAN 기반의 A/V 전송용 변복조 모뎀 설계 (Design of WLAN-based A/V System for Multimedia Home Networks)

  • 이연성;김현식;위정욱;백종호
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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    • pp.327-330
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    • 2008
  • This paper shows an implementation of WLAN-based Audio/Video(A/V) system for multimedia home networks. Proposed WLAN-based A/V system can transmit multimedia data of high quality. The entire system consists of a 16-bit RISC controller, a program ROM, a SRAM, timers, an interrupt controller, a DART, GPIOs, an I2C and the OFDM modem supporting for the IEEE 802.11g standard. The simple MAC functions are implemented by firmware on an embedded 16-bit RISC controller. The OFDM modem supports a complete set of data rates up to 54Mbps. Proposed the system is implemented by an Altera FPGA EP1S60F1020C6 device, a 10-bit 2-ch DAC, a 10-bit 2-ch ADC and RF/IF chips.

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