• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1093-1096
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• 1999

In this paper, video image segmentation algorithm based on color histogram and change detector is proposed. Color histograms are calculated from both changed region which is detected in the previous and current frame and unchanged region. With each histogram, modes and valleys are detected. Then, color vectors are calculated by averaging pixels in modes. Markers are extracted by labeling color vectors that represent modes, the watershed algorithm is applied to determine uncertain region. In growing region, the root mean square(RMS) of the distance between average pixel in marker region and adjacent pixel is used as a measure. The proposed algorithm based on color histogram and change detector segments video image fastly and effectively. And simulation results show that the proposed method determines the exact boundary between background and foreground.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of Astronomy and Space Sciences
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• v.10 no.1
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• pp.86-93
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• 1993

We experiment of the method to obtain the uniform gas multiplication in multiwire proportional counter. The general techenique of anode wire connection for the high voltage supply could not secure the uniformity of multiplication because of the edge effect at the outer anode wires. We found that the variation of the multiplication could be corrected in the accuracy of $\pm$1.6% rms using the voltage compansation method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• Bulletin of the Korean Space Science Society
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• 2011.04a
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• pp.30.2-30.2
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• 2011

In this report, we present in-orbit radiometric performance prediction for the Amon-Ra (Albedo Monitor and Radiometer) energy channel instrument. The Integrated Ray Tracing (IRT) computational technique uses the ray sets arriving at the Amon-Ra instrument aperture orbiting around the L1 halo orbit. Using this, the variation of flux arriving at the energy channel detector was obtained when the Amon-Ra instrument including the energy channel design observes the Sun and Earth alternately. The flux detectability was verified at the energy channel detector (LME-500-A, InfraTecTM). The detector time response and RMS signal voltage were then derived from the simulated flux variation results. The computation results demonstrate that the designed energy channel optical system satisfies the in-orbit detectability requirement. The technical details of energy channel instrument design, IRT model construction, radiative transfer simulation and output signal computation results are presented together with future development plan.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.766-776
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• 2015

It is well known that series arc faults in Low Voltage DC (LVDC) distribution system occur at unintended points of discontinuity within an electrical circuit. These faults can make circuit breakers not respond timely due to low fault current. It, therefore, is needed to detect the series fault for protecting circuits from electrical fires. This paper proposes a novel scheme to detect the series arc fault using Wavelet Singular Value Decomposition (WSVD) and state diagram. In this paper, the fault detector developed is designed by using three criterion factors based on the RMS value of Singular value of Approximation (SA), Sum of the absolute value of Detail (SD), and state diagram. LVDC distribution system including AC/DC and DC/DC converter is modeled to verify the proposed scheme using ElectroMagnetic Transient Program (EMTP) software. EMTP/MODELS is also utilized to implement the series arc model and WSVD. Simulation results according to various conditions clearly show the effectiveness of the proposed scheme.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• Journal of Radiation Protection and Research
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• v.39 no.2
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• pp.81-88
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• 2014

Recently, a new imaging method, gamma vertex imaging (GVI), was proposed for the verification of in-vivo proton dose distribution. In GVI, the vertices of prompt gammas generated by proton induced nuclear interaction were determined by tracking the Compton-recoiled electrons. The GVI system is composed of a beryllium electron converter for converting gamma to electron, two double-sided silicon strip detectors (DSSDs) for the electron tracking, and a scintillation detector for the energy determination of the electron. In the present study, the modules of a charge sensitive preamplifier (CSP) and a shaping amplifier for the analog signal processing of DSSD were developed and the performances were evaluated by comparing the energy resolutions with those of the commercial products. Based on the results, it was confirmed that the energy resolution of the developed CSP module was a little lower than that of the CR-113 (Cremat, Inc., MA), and the resolution of the shaping amplifier was similar to that of the CR-200 (Cremat, Inc., MA). The value of $V_{rms}$ representing the magnitude of noise of the developed system was estimated as 6.48 keV and it was confirmed that the trajectory of the electron can be measured by the developed system considering the minimum energy deposition ( > ~51 keV) of Compton-recoiled electron in 145-${\mu}m$-thick DSSD.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.10 no.5
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• pp.101-107
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• 1996

This paper proposed the voltage compensation analysis method in distribution system by EMTP. SVC (Static Var Compensator) of the thyristor controlled reactor type is used for compensation system. EMTP(E1ectr-o Magnetic Transient Program) model of SVC is proposed to analysis the voltage improvement characteristics at the high voltage system bus. It is composed with three parts ; rms detector, voltage regulator and gate pulse generator. The control signal of TCR is determined by rms value which was measured in system. As the result of EMTP simulation, all of the SVC characteristics like TCR current, firing pulse and bus voltage is very reliable. This method could be used to analysis the planning and the operation of compensation system in the large scale factory.