• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.809-812
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• 2013

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1413-1421
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• 2014

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.493-496
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• 2010

This paper proposes an effective hardware scheme for thinning stage processing of a fingerprint identification algorithm based on minutiae with 40% cycle occupation of 32-bit RISC microprocessor. The thinning step is needed to be processed by hardware block, because it is performed repeatedly by processing the same operation using an image window masking method. It can reduce the burden of the system and improve speed. The hardware is implemented by HDL and simulated. The result is compared with a conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of IKEEE
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• v.19 no.1
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• pp.52-57
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• 2015

The disease diagnosis system has been developed using the thin nitride(Si3N4) cantilever arrays which can measure the difference of capacitances between sensor and reference. The system consists of 32-bits RISC(Reduced Instruction Set Computer), RAM/Flash, bus, communication IP's, ADC(Analog Digital Converter) board, and LCD display. The marker selection method, which give us the good accuracy from reasonal numbers of markers, is suggested. The developed system has the resolution under 1fF and can detect 10nM concentration of Thrombin.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.273-279
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• 2001

This paper describes a design and implementation of ISDN system on a chip which provides ISDN service and used to develop a low-price multimedia communication terminal. This ISDN SOC is an ISDN system control chip which has 32bit RISC processor, and it includes ISDN S interface transceiver, G.711 voice CODEC, PC interface for data communication, ISDN protocol which includes Q.931 call control protocol and internet protocol. It provides good solution to develope ISDN terminal equipment and ISDN terminal adaptor which connected with basic rate interface, because it minimize external peripheral devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.