• Title/Summary/Keyword: RISC

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32 Bit RISC Core modeling using SystemC

  • 최홍미;박성모
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.325-328
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    • 2002
  • In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).

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Developing of HW/SW Co-Design and Verification Environment for Information-App1iance-On-a-Chip (정보기기온칩을 위한 HW/SW 혼합 설계 및 검증 환경 개발)

  • 장준영;신진아;배영환
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.117-120
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    • 2001
  • This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

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Design and Verification of an ARM7 Compatible 32-bit RISC Processor (ARM호환 32비트 RISC 프로세서의 설계 및 검증)

  • 배영돈;서보익;이용석;박인철
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.416-420
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    • 1999
  • This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

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A Desigen of the ARM7-Compatible 32Bit RISC Microprocessor (ARM7 호환 32-Bit RISC Microprocessor 설계)

  • 이기호;유영재;김기민;강용호;송호준;이철훈
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10a
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    • pp.18-20
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    • 1998
  • 본 논문에서는 RISC Microprocessor Core 설계에 대한 기반 기술을 확립하여, GPS(Global Positioning System) 같은 Embedded 시스템 등에서 주로 사용되어 지고 있는 ARM사의 ARM7 CPU와 이진 호환이 가능한 Microprocessor를 설계하고자 하였다. 이를 위하여 RISC Microprocessor의 기본적인 구조를 바탕으로 하여 ARM7 CPU와의 호환을 위하여 ARM7 CPU의 명령어들이 주어진 Clock안에 수행될 수 있도록 설계를 하였고, 여러 모듈을 원활히 공유할 수 있도록 내부에 공유 버스를 설계하였다. 설계를 위해서 Verilog-HDL(Hardware Description Language)을 사용하였으며, Microprocessor를 기술하는데 있어서 Behavioral 구조와 RTL(Register Transfer Level) 구조를 혼합하여 사용하였다. 설계된 Microprocessor의 동작은 면적과 타이밍의 최적화를 거친 후 Cwaves 툴을 사용하여 실질적인 ARM7의 명령어들을 수행하면서 검증하였다.

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Implementation of a 32-Bit RISC Core for Multimedia Portable Terminals (멀티미디어 휴대 단말기용 32 비트 RISC 코어 구현)

  • 정갑천;기용철;박성모
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.226-229
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    • 2000
  • In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

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Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

  • Jung, Hong-Kyun;Jin, Xianzhe;Ryoo, Kwang-Ki
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.78-84
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    • 2012
  • This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

A VLSI implementation of 32-bit RISC embedded controller (내장형 32비트 RISC 콘트롤러의 VLSI 구현)

  • 이문기;최병윤;이승호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.141-151
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    • 1994
  • this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

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The Design of A Machine-independent Global Optimizer for RISC Compilers (RISC 컴파일러의 기계독립적 Global Optimizer 설계)

  • Park, Jong-Deuk;Lim, In-Chil
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.3
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    • pp.40-46
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    • 1990
  • This paper describes a design and an implementation of a machine-independent global optimizer which is a required module of RISC compiler system designs. It receives a triple as input and performs data flow analysis, common subexpression elimination and code motion and finally generates the optimized code. Since the implemented optimizer operates on the machine-independent intermediate code, its portability is good for many high level languages and target machines. It performs the effective optimizations to improve the execution time of programs.

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A Study on the 32 bit RISC/DSP Microprocessor Appropriate for Embedded Systems (내장형 시스템에 적합한 32 비트 RISC/DSP 마이크로프로세서에 관한 연구)

  • 유동열;문병인;홍종욱;이태영;이용석
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.257-260
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    • 1999
  • We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

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Desing of A RISC-Processor's Control Unit (RISC 프로세서 제어부의 설계)

  • 홍인식;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.7
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    • pp.1005-1014
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    • 1990
  • This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

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