Implementation of a 32-Bit RISC Core for Multimedia Portable Terminals

멀티미디어 휴대 단말기용 32 비트 RISC 코어 구현

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.