• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.62-64
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• 2004

초고속 RF IC의 핵심소자인 SiGe에피텍시층을 가진 이종양극트란지스터 (hetero junction bipolar transistor: HBT)를 0.35um급 CMOS공정으로 제작하였다. 이때 IOW $V_{BE}$영역에서의 Current Gain의 선형성을 향상시키기 위하여 Capping 실리콘의 두께를 200과 300${\AA}$으로 나누고 EDR (Emitter Drive-in RTA)의 온도와 시간을 900$\~$1000C, 0$\~$30sec로 각각 변화시키면서 최적조건을 알아보았다. 실험범위 내에서의 최적공정조건은 300${\AA}$의 capping 실리콘과 975C-30sec의 EDR조건이었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.258-258
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• 2007

일반적인 CMOS공정으로는 높은 주파수 대역에서 높은 Q factor를 갖는 인덕터를 구현하는데 어렵고 이에 반해 RF ICs는 갈수록 high Q를 가지는 인덕터가 요구되고 있다. 이를 LTCC 기판 위에 인덕터를 구현했을 때 놓은 주파수 대역에서 성능을 알아보기 위해 모의 실험하였고, 실제로 구현을 하여 측정결과를 비교해 보았다. LTCC 기판위에 인덕터를 구현 하였을 때 실리콘, 유리 기판위에 인덕터를 구현하였을 때보다 더 높은 Q 값을 측정할 수 있었다. 5GHz 대역에서 실리콘, 유리, LTCC 기판에서 각각 12, 33, 51에 값을 확인할 수 있었다.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.345-345
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• 2012

최근 의료산업에서는 고해상도 및 동영상 구현이 가능한 직접 방식의 X-선 검측센서에서 X-ray 흡수효율이 좋은 반도체 센서(CdTe, CdZnTe 등)와 성숙된 기술, 집적효율이 뛰어난 CMOS 공정을 이용한 제품을 출시하여 대면적화 및 고집적화가 가능하게 되어 응용분야가 점차 확대되고 있는 추세이다. 하지만 이 역시 고 성능의 X-선 동영상 구현을 위해서는 고 해상도 문제, 검출효율 문제, 대면적화의 어려움이 있다. 기존의 X-선 광 도전층의 증착은 증착 속도와 박막 품질에서 우수한 Evaporation 법이 사용되고 있다. 한편, 대면적에 균일한 박막형성이 가능하기 때문에 양산성에서 우월성을 가지는 sputtering법의 경우, 밀도가 높은 소결체 타겟의 제조가 힘들뿐만 아니라 증착 속도가 낮아 장시간 증착 시 낮은 소결밀도로 인한 타겟 Particle 영향으로 인해서 대 면적에 고품질의 박막을 형성하기가 어렵다. 하지만 최근 소결체 타겟 제조기술 발달과 함께, 대면적화와 장시간 증착에 대한 어려움이 해결되고 있어 sputtering 법을 이용한 고품질 박막 제조 기술의 연구가 시급한 실정이다. 본 연구에서는 $50{\times}50$ mm 크기의 non-alkali 유리기판(Corning E2000) 위에 Evaporation과 RF magnetron sputtering을 사용하여 다양한 기판온도 (RT, 100, 200, 300, $350^{\circ}C$)에서 $1{\mu}m$의 두께로 CdTe 박막을 증착하였다. RF magnetron sputtering의 경우 CdTe 단일 타겟(50：50 at%)을 사용하였으며 Base pressure는 약 $5{\times}10^{-6}$ Torr 이하까지 배기하였고, Working pressure는 약 $7.5{\times}10^{-3}$ Torr에서 증착하였다. 시편과 기판 사이의 거리는 70 mm이며 RF 파워는 150 W로 유지하였다. CdTe 박막의 미세구조는 X-ray diffraction (XRD, BRUKER GADDS) 및 Field Emission Scanning Electron Microscopy (FE-SEM, Hitachi)를 사용하여 측정하였다. 또한, 조건별 박막의 조성은 Energy Dispersive X-ray Spectroscopy (EDS, Horiba, 7395-H)을 사용하여 평가하였다. X-선 동영상 장치의 구현을 위해서는 CdTe 다결정 박막의 높은 흡수효율, 전하수집효율 및 SNR (Signal to Noise Ratio) 등의 물성이 요구된다. 이러한 물성을 나타내기 위해서는 CdTe 박막의 높은 결정성이 중요하다. Evaporation과 RF magnetron sputtering로 제작된 CdTe 박막은 공정 온도가 증가함에 따라 기판상에 도달하는 스퍼터 원자의 에너지 증가로 인해서 결정립이 성장한 것을 확인할 수 있었다. 따라서 CdTe 박막이 직접변환방식 고감도 X-ray 검출기 광도 전층 역할을 수행할 수 있을 것으로 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.89-94
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• 2008

In this paper, a cascade of a wideband amplifier and a high-Q bandpass filter (BPF) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion receivers. The wideband amplifier is designed to obtain the -3dB bandwidth of 5.4GHz, and the high-Q BPF is designed to select a 2.4GHz RF signal for the Bluetooth specifications. The measured results demonstrate 18.8dB power gain at 2.34GHz with 31MHz bandwidth, corresponding to the quality factor of 75. Also, it shows the noise figure (NF) of 8.6dB, and the broadband input matching (S11) of less than -12dB within the bandwidth. The whole chip dissipates 64.8mW from a single 1.8V supply and occupies the area of $1.0{\times}1.0mm2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.90-95
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• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.43-50
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• 2016

In this paper, new automatic LC calibrator is proposed for realizing a passive LC filter with almost constant frequency characteristic regardless of the PVT variations. The SAW-less GPS RX front-end is implemented using a 65nm CMOS process using the proposed LC calibrator. Also, new dual-mode low noise amplifier (LNA) structure is proposed to generate the RF signal required for the LC calibrator. The characteristics of the implemented GPS RX front-end show the voltage gain of about 42.5 dB, noise figure of below 1.35 dB, the blocker input P1dB of -24 dBm in case of the worst blocker signal at 1710 MHz frequency, while it consumes 7 mA current at 1.2 V power supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.67-67
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• 2009

Due to the scaling down of the dielectrics thickness, the leakage currents arising from electron tunneling through the dielectrics has become the major technical barrier. Thus, much works has focused on the development of high k dielectrics in both cases of memories and CMOS fields. Among the high-k materials, $Al_2O_3$ considered as good candidate has been attracting much attentions, which own some good properties as high dielectric constant k value (~9), a high bandgap (~2eV) and elevated crystallization temperature, etc. Due to the easy control of ion energy and flux, low ownership and simple structure of the inductively coupled plasma (ICP), we chose it for high-density plasma in our study. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of BClxOy compound. In this study, the etch characteristic of ALD deposited $Al_2O_3$ thin film was investigated in $BCl_3/N_2$ plasma. The experiment were performed by comparing etch rates and selectivity of $Al_2O_3$ over $SiO_2$ as functions of the input plasma parameters such as gas mixing ratio, DC-bias voltage and RF power and process pressure. The maximum etch rate was obtained under 15 mTorr process perssure, 700 W RF power, $BCl_3$(6 sccm)/$N_2$(14 sccm) plasma, and the highest etch selectivity was 1.9. We used the x-ray photoelectron spectroscopy (XPS) to investigate the chemical reactions on the etched surface. The Auger electron spectroscopy (AES) was used for elemental analysis of etched surface.