• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1905-1913
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• 2006

The researches about the hardware and the software implementing ubiquitous sensor network have great rush in recent years. This paper deals the development of a sensor node with the dual interface which also has an RF wireless interface while has an Bluetooth interface used widely in present. This sensor node includes a Atmeg32 microcontroller, a Bluetooth module, a RF module. a temperature-humidity sensor. and I also develop the F/Ws controlling each modules with C language using GCC compiler. The sensor node developed can reaches 15m with Bluetooth interface and 60m with RF interface. It works stably with the voltage above 5V and it consumes currents 21mA average in idle mode, 63mA average in active mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.2
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• pp.149-158
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• 2024

Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.411-414
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• 2004

This paper introduces a modulation method for digital wireless communication based on general DS-QPSK. The design and fabrication is for home networking application to a typical RF transmitter with DS-QPSK modulator. This modulator implemented using VHDL hardware programming language, the fabrication of IC chip $5{\times}5 mm^2$ was carried by 27th IDEC MPW(Multi Project Wafer) process in 0.35${\mu}m$ rule at Samsung Inc. This paper presented the important of this technology for the future application in wireless sensor. This module can be efficient usage for home network to transmit the RF wireless sensor system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1061-1068
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• 2013

In this paper, we propose a $M{\times}M$ beam-space multiple input multiple output (BS-MIMO) system using electronically steerable parasitic array radiator (ESPAR) antenna. Conventional MIMO method required multiple RF chains because it map the transmission signals onto multiple antennas. So, conventional MIMO system has high cost for design and high energy consumption at RF circuit. Also, It is difficult to use MIMO system in battery based mobile terminals with limited physical area. In order to solve these problems, BS-MIMO technique which map the data signal onto bases in beam space domain was proposed using ESPAR antenna with single RF chain. This paper, we design and analyze the performance of extended $M{\times}M$ BS-MIMO technique. Simulation results show that the proposed BS-MIMO system has similar BER performance compare to conventional MIMO scheme. Therefore, BS-MIMO system with single RF chain will has a low RF power consumption and low cost for RF hardware design as compared with conventional MIMO technique with multiple RF chains.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.39-45
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• 2011

In this paper, the design method of portable signal analysis system is proposed and the hardware module is implemented for operation of base stations based on a common platform for mobile WiMax. The new signal analysis method is implemented as two modules; a broadband RF module and a DSP based digital signal analysis module. The RF module performs the RF-IF down conversion and gain control. And the digital module measure the base staion signal. The differences of performance are insignificant in the experiment results performed through the comparison of other fixed-large system and proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1252-1263
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• 2009

In this paper, in order to improve a service quality and to broaden the service coverage in the mobile communication system a study on a digital RF repeater employed with an Interference Cancellation System(ICS) is performed. The digital RF repeater employed with an ICS is implemented to remove interference and feedback signals which are disadvantages of a conventional(or general) RF repeater. This thesis presents the design and experiments of the new wireless repeater. The proposed wireless repeater consists of a RF repeater mounted with digital engine. The digital ICS engine consists of a DSP and FPGA. The digital engine and RF circuit are designed into a one-piece. After developing hardware through the digital platform they are also designed and fabricated into a one-piece in order to apply a best performance repeater system. The method of removing interference and feedback signals is an adaptive IF technique employed with a LMS algorithm. The powerful performance and fast convergence speed is obtained by using this method.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2239-2241
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• 2003

A new RF control system of Pohang Accelerator Laboratory (PAL) storage ring is a subsystem upgraded PAL control system, which is based upon Experimental Physics and Industrial Control System (EPICS). There are 5 control components, Low Level RF System (LRS), Klystron System, Circulator System, Cavity System, Local Cooling Water System (LCW) at the storage ring of PAL. The new RF control system for the storage ring has been under development for one years, first versions of individual VME (Versa Module Europa) Input/output modules under construction and system integration begun. In this system, VMEbus-based hardware is widely used for front-end controllers (FDS), Input/output controller (IOC). A number of Programmable Logic Controller (PLC) and SUN workstations are also used for Operator Interfaces (OPI) in the control system. This paper describes the development VME I/O module to the new control system and how the design of this new system.