• 전자공학회논문지B
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• 제32B권12호
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• pp.1572-1580
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• 1995

In this paper, a modified Chebyshev low-pass filter function is proposed. The modified Chebyshev filter function exhibits ripples diminishing toward .omega. = 0 in the passband. So, the modified filter function is realizable in the passive doubly-terminated ladder network for the order n even or odd, thus lending itself amenable to active RC or switched capacitor filters through the simulation techniques. Besides the passive doubly-terminated ladder realizability, lower pole-Q values of the modified function are accountable for improved phase and delay characteristics, as compared to classical function. We have designed the 6th order passive doubly-terminated network using the modified function. And then a continuous-time DDA(Differential Difference Amplifier) filter, which has no matching requirement, is realized by leap-frog simulation technique for fabrication. In the HSPICE simulation results, we confirmed that the designed continuous-time DDA filter characteristics are agreement with the passive filter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.671-677
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• 2015

A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor ${\alpha}$, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor ${\alpha}$ an attractive option for lower power applications.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.48.1-48.1
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• 2010

Cu has been used for metallic interconnects in ULSI applications because of its lower resistivity according to the scaling down of semiconductor devices. The resistivity of Cu lines will affect the RC delay and will limit signal propagation in integrated circuits. In this study, we investigated the characteristics of electroplated Cu films according to the variation of concentration of organic additives. The plating electrolyte composed of $CuSO_4{\cdot}5H_2O$, $H_2SO_4$ and HCl, was fixed. The sheet resistance was measured with a four-point probe and the material properties were investigated with XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope) and XPS (X-ray Photoelectron Spectroscopy). From these experimental results, we found that the organic additives play an important role in formation of Cu film with lower resistivity by EPD.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.207-209
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• 2018

본 논문은 고효율 및 고전력밀도 3-레벨 PFC(Power Factor Correction) 컨버터를 제안한다. 기존 PFC의 고 전력밀도를 위한 스위칭 주파수 상승은 스위칭 특성이 우수한 소자를 적용하거나, 별도의 스너버 회로가 요구되므로 설계가 복잡하며 고전력밀도 달성에 한계가 있다. 제안 PFC 컨버터는 3-레벨 방식을 적용하여 각 스위칭 소자의 전압 스트레스를 절반으로 감소시켰으며, 스위치 손실 저감을 통한 고속 스위칭 동작으로 리액티브 소자의 고밀도화를 달성하였다. 또한, 기존의 3-레벨방식은 디지털 제어를 통해 스위칭 소자의 전압 평형이 이루어졌지만, 본 논문에서는 아날로그 IC에 전압 평형을 위한 RC Delay 회로와 소수의 SMD(Surface-mount devices) 소자만을 이용하여 별도의 제어회로 없이 전압 평형이 가능하므로 고 전력밀도 달성에 유리하다. 제안회로의 타당성을 검증하기 위해 CRM(Critical conduction mode) PFC 컨버터를 기반으로 250W급 시작품 제작을 통한 실험 결과를 제시한다.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권2호
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• pp.202-215
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• 2013

This paper proposes a SEPIC-input, self-driven, active clamp ZVS converter, where an auxiliary winding and a RC delay circuit are employed to drive the active clamp switch and to achieve asymmetrical duty control without any other extra circuits. Based on the fixed dead time and the resonance between capacitors and inductors, both the main switch and the auxiliary switch can rule the ZVS operation. Detailed operation modes are presented to illustrate the self-driven and ZVS principles. Furthermore, an accurate state-space model and the transfer functions of the proposed converter have been presented and analyzed in order to optimize dynamic performance. The model provides efficient prediction of converter operations. Experimental results, based on a prototype with 80V input and 15V/20A output, are discussed to verify the transient and steady performance of the proposed converter.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2011년도 춘계학술대회 및 Fine pattern PCB 표면 처리 기술 워크샵
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• pp.175-177
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• 2011

오늘날 반도체 소자의 성능을 좌우하는 배선폭은 수십 나노미터급으로 배선폭 감소에 의한 소자의 집적은 한계에 다다르고 있다. 또한 2차원 회로 소자의 문제점으로 지적되는 과도한 전력소모, RC Delay, 열 발생 문제등도 쟁점사항이 되고 있다. 이런 2차원 회로를 3차원으로 쌓아올린다면 보다 효율적인 회로구성이 가능할 것이고 이에 따른 성능향상이 클 것이다. 3차원 회로 구성의 핵심기술은 기판을 관통하여 다른 층의 회로를 연결하는 실리콘 관통 전극을 형성하는 것이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.173-176
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• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.40-40
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• 2000

직접 회로의 소자크기가 더욱 미세화에 따라, 기존에 사용하는 금속 배선의 저항과 금속 배선과 층간 유전 물질에 의한 정전용량의 증가로 인한 시간 지연 (RC time delay) 문제가 크게 대두되고 있다. 이 문제를 해결하기 위해 비유전율이 낮은 물질을 층간 유전체로 사용하여 정전용량을 낮추는 것이 필요하다. 기존의 실리콘 산호막 대신에 MSSQ(methylsilsequioxance)를 이용할 때 필요한 건식 식각 공정을 연구하였다. MSSQ 물질을 patterning 하기 위해 습식 공정의 부산물인 폐액 등의 문제점이 발생하지 않을 뿐만 아니라, 소자의 손상이 적고 선택비가 높으며, 식각의 이방성을 향상시킬 수 있는 장점을 갖고 있는 반응 이온 식각기(reactive ion etchin)을 이용하였다. CF4/O2 plasma를 사용하였는데, 가스의 양의 flow rate와 조성비, RF pover(50, 100, 150 W)등의 변화에 따른 식각 특성을 알아보았다. atep, SEM, AFM등을 이용하여 측정·분석하였다.