• 제목/요약/키워드: RC delay

검색결과 113건 처리시간 0.024초

램프 입력에 대한 RC-class 연결선의 지연시간 예측을 위한 해석적 연구 (An Analytic Study on Estimating Delay Time in RC-class Interconnects Under Saturated Ramp Inputs)

  • 김기영;김승용;김석윤
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권4호
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    • pp.200-207
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    • 2004
  • This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

RC-class 연결선의 축소모형을 이용한 대수적지 연시간 계산법 (Algebraic Delay Metric Using Reduced Models of RC Class Interconnects)

  • 김승용;김기영;김석윤
    • 대한전기학회논문지:시스템및제어부문D
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    • 제52권5호
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    • pp.193-193
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    • 2003
  • This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

RC-class 연결선의 축소모형을 이용한 대수적지 연시간 계산법 (Algebraic Delay Metric Using Reduced Models of RC Class Interconnects)

  • 김승용;김기영;김석윤
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권5호
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    • pp.193-200
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    • 2003
  • This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

RC tree의 지연시간 예측 (RC Tree Delay Estimation)

  • 유승주;최기영
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.209-219
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    • 1995
  • As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

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램프 입력에 대한 RC-class 연결선의 누화잡음을 고려한 지연시간 예측 기법 (A Simple Technique on Estimating Delay Time Considering Crosstalk Noise in RC-class Interconnects Under Saturated Ramp Input)

  • 김기영;오경미;김석윤
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제54권7호
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    • pp.299-303
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    • 2005
  • This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

삼각함수형 RC분포회로의 과도응답해석 (Transient Response Analysis of the Trigonometric Distributed RC Circuit)

  • 김덕진
    • 대한전자공학회논문지
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    • 제4권4호
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    • pp.13-18
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    • 1967
  • 삼각함수형 선형 수동 RC분포회로의 전압전달함수의 모든 극점은 s-평면상에서 부의 실축상에 존재하므로 unit step input에 대한 과도응답은 단조한 특성을 갖는다. 이러한 특성은 집중정수회로에 적용하였던 Elmore의 상승시간 및 지연시간 계산방법을 RC분포회로에도 적용시킬 수 있는 충분한 조건이므로 본 논문에서는 삼각함수형 RC분포회로의 과도응답특성해석을 위의 방법으로 시도하였다. 그 결과 이 회로의 상승시간 및 지연시간은 시정수 및 거리각 θ의 증가와 더불어 이들 시간도 증가함을 확인하였다.

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램프 입력에 대한 RC-class 연결선의 누화잡음을 고려한 지연시간 예측 기법 (A Simple Technique on Estimating Delay Time Considering Crosstalk Noise in RC-class Interconnects Under Saturated Ramp Input)

  • 오경미;김기영;김석윤
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.573-576
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    • 2004
  • This paper proposes an analytic method that can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

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Delay Switching PLL의 Pull-in 특성 (Pull-in Characteristics of Delay Switching Phase-Locked Loop)

  • 장병화;김재균
    • 대한전자공학회논문지
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    • 제15권5호
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    • pp.13-18
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    • 1978
  • 본 논문에서는 PLL의 pull-in 특성을 개선하기 위하여 delay switching PL난을 제시하였다. phase detector와 low grass filter사이에 간단한 RC delay회로를 삽입하고, 90° shift 시킨 Phase detector출력에 의하여 delay time을 switching하였다. 그 결과 pull-in range는 lock range의 1/2이상으로 넓힐 수 있었으며 pull-in time도 개선되었다. 이 개선된 Pull-in특성은 근사적으로 해석되었으며 실험으로 확인되었다.

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Development of a variable resistance-capacitance model with time delay for urea-SCR system

  • Feng, Tan;Lu, Lin
    • Environmental Engineering Research
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    • 제20권2호
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    • pp.155-161
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    • 2015
  • Experimental research shows that the nitric oxides ($NO_X$) concentration track at the outlet of selective catalytic reduction (SCR) catalyst with a transient variation of Adblue dosage has a time delay and it features a characteristic of resistance-capacitance (RC). The phenomenon brings obstacles to get the simultaneously $NO_X$ expected to be reduced and equi-molar ammonia available to SCR reaction, which finally inhibits $NO_X$ conversion efficiency. Generally, engine loads change frequently, which triggers a rapid changing of Adblue dosage, and it aggravates the air quality that are caused by $NO_X$ emission and ammonia slip. In order to increase the conversion efficiency of $NO_X$ and avoid secondary pollution, the paper gives a comprehensive analysis of the SCR system and tells readers the key factors that affect time delay and RC characteristics. Accordingly, a map of time delay is established and a solution method for time constant and proportional constant is carried out. Finally, the paper accurately describes the input-output state relation of SCR system by using "variable RC model with time delay". The model can be used for a real-time correction of Adblue dosage, which can increase the conversion efficiency of $NO_X$ in SCR system and avoid secondary pollution forming. Obviously, the results of the work discover an avenue for the SCR control strategy.

클러스터를 이용한 고성능 RC4 암호화 하드웨어 설계 (The Design of a High-Performance RC4 Cipher Hardware using Clusters)

  • 이규희
    • 한국정보통신학회논문지
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    • 제23권7호
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    • pp.875-880
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    • 2019
  • RC4 스트림 암호화는 내부 구현이 간단하고 빠르게 암호화 할 수 있는 초경량 암호화 알고리즘으로 IEEE 802.11의 WEP와 IEEE 802.11i의 TKIP 등에 널리 이용되고 있다. RC4는 IoT 등의 제한적 자원을 갖는 시스템들에도 사용되지만 성능상 제약이 있다. RC4 암호화는 S-배열과 K-배열의 초기화 및 랜덤화를 수행하는 KSA(Key Scheduling Algorithm)와 랜덤화된 S-배열을 이용하여 암호문을 생성하는 PRGA(Pseudo-Random Generation Algorithm)의 두 단계로 구성된다. 본 논문에서는 KSA에서 발생하는 초기화 지연시간을 줄이기 위해, 랜덤화 과정에 초기화를 삽입하여 함께 처리한다. KSA의 랜덤화에서 교환(swap) 작업과 PRGA의 암호문 생성은 클러스터를 이용하여 매 클록마다 두 개의 교환 및 암호문이 생성되도록 하였다. 제안된 RC4 암호화 하드웨어 구조는 초기화 지연시간이 발생하지 않으며, 랜덤화와 키 스트림 생성율에서 다른 연구들과 비교하여 약 2배에서 6배의 성능이 향상되었다.