• 제목/요약/키워드: R-C circuit

검색결과 288건 처리시간 0.023초

R-C 분포회로에 관한 연구 (Research on R-C Distributed Circuits)

  • 박송배
    • 대한전자공학회논문지
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    • 제3권2호
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    • pp.10-17
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    • 1966
  • 어떤 R-C 분포회로의 징분방정식의 해가 기지일 때 이것을 이용하여 다수의 다른 분포회로의 징분방정식의 해를 구하는 방법이 얻어졌다. 임의의 R-C 분포회로를 제작의 편의상 R(x)C(x)=일정인 회로로 등가변환하는 도해적방법이 얻어졌으며 해석적증명도 가능하다. 또 이론적 취급의 통일과 간단을 위하여 임의의 R-C분포회로를 R(x), C(x) 어느 한쪽이 일정한 분포회로로 등가변환하는 방법이 얻어졌다. 이 후자의 회로와 근사적인 집중정수회로를 생각하므로서 분포회로의 근사적인 해석, 합성이 비교적 간단하게 이루어 질 수 있다. 6x A method by which solutions of the differential equations of any other distributed circuits can be obtained is described when the solution of the differential equation of an R-C distributed amplifier is known. A graphical method of transforming any R-C ditributed circuit into an equivalent circuit which has a constant R(x)-C(x) was also obtained. The theoretical verification of this method is possible. For simplicity, any R-C distributed circuit can be transformed into an equivalent circuit which is a distributed circuit of either constant R(x) or C(x). Using this equivalent circuit and considering a lumped circuit, an approximate analysis and synthesis can be made simply.

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L성분이 없는 간략화 Chua 회로 구현에 관한 연구 (A Study on implementation of Simplify Chua's Circuit without L component)

  • 손영우;배영철
    • 한국전자통신학회논문지
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    • 제5권1호
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    • pp.17-22
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    • 2010
  • 일반적으로 카오스 회로에는 Chua's 회로, Lorenz 회로, Duffing 회로 등이 있다. 이들 카오스 회로 중에서 Chua's 회로가 전자부품을 이용하여 가장 쉽게 구성할 수 있는 회로로 알려져 있다. Chua's 회로는 일반적으로 저항성분인 R, 인턱터 성분인 L, 캐패시터 성분인 C로 구성하는 선형요소와 비선형 저항으로 구성하는 비선형 요소로 구성된다. 그러나 L 요소는 포화특성으로 인하여 시중에서 구입한 부품으로는 실제 하드웨어를 구현하기 어려운 문제점이 있다. 본 연구에서는 Chua 회로의 선형 요소인 R,L,C 성분의 요소 중에서 포화 특성을 자지고 있어 상용화된 제품으로는 제작 구현이 어려운 L 성분을 C 성분으로 대체하는 간략화한 Chua's 회로 제작 기법을 PSpice로 해석하고, 그 결과를 확인한다.

방사선조사에 의한 R-C 직.병렬회로에서의 손상효과에 관한 연구 (A Study on Irradiation Effect by $Co^{60}$ of the R-C Series-Parallel Circuits)

  • 서국철;조성욱
    • 한국조명전기설비학회지:조명전기설비
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    • 제1권2호
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    • pp.57-61
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    • 1987
  • 원자력 산업에서 사용되고 있는 모든 재료의 특성은 방사선조사에 의한 손상효과로 변하게 된다. 본 연구에서는 저항과 콘덴서의 직.병렬회로에서의 방사선조사에 의한 전기적 특성이 여하히 변화되는가를 연구하였다. 연구결과 얻어진 주요 결론은 다음과 같다. 1. R-C 직렬회로에서 조사선량이 $10^6[r]$까지는 임피던스변화율이 증가되다가 그 이상의 조사선량에서는 포화상태에 이르게 되는데 포화상태에서의 증가율은 1.25[%]정도이었다. 2. R-C 직렬회로에서 조사선량이 $10^6[r]$ 까지는 증가변화율이 감소되다가 그 이상의 조사선량에서는 포화상태에 이르게 되는데 감소율은 0.5[%]정도이었다. 3. R-C 병렬회로에서는 방사선량이 $10^6[r]$까지는 임피던스변화율이 증가되다가 그 이상의 방사선량에서는 포화상태에 이르게 되는데 증가율은 0.5[%]정도이었다. 4. R-C 병렬회로에서는 방사선량이 $10^6[r]$까지는 감소되다가 그 이상의 방사선량에서는 포화상태에 이르게 되는데 감소율은 1.3[%]정도이었다.

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부품이 실장된 전자회로보드의 RLC 병렬회로 검사기법에 대한 연구 (A Study on the Test Method of RLC Parallel Circuits on the Device-Mounted Electronic Circuit Board)

  • 고윤석
    • 대한전기학회논문지:시스템및제어부문D
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    • 제54권8호
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    • pp.475-481
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    • 2005
  • In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

저압차단기기의 보호협조 (The Protective Co-ordination between Low-Voltage Circuit-Breaker)

  • 박성찬;오준식;이방욱;유만종;서정민
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 추계학술대회 논문집 전력기술부문
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    • pp.340-343
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    • 2001
  • In an electrical network, electrical power are transmitted by a various of protection, isolation and control electric circuit devices. This thesis deals with the protection function between circuit-breakers. The protective coordination concerns the behaviour of two devices placed in series in an electrical network, with a short-circuit downstream circuit-breaker. It has two basic principles: First, discrimination which is an increasing requirement of low voltage electrical distribution systems. Second, which is less well known: cascading, which consists of installing a device, whose breaking capacity is less than the three-phase short-circuit current at its terminals and helped by main circuit-breaker. The important advantage of cascading is to be able to install at a branch circuit-breaker of a lesser performance without endangering the safety of the installation for more economical usage. To determine and guarantee co-ordination between two circuit breakers, it is necessary to carry out a theoretical approach, first, and then confirm the results by means of standard tests. This is illustrated in appendix A of IEC 947-2.

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$ITO/TPD/Alq_3/Al$ 유기발광소자의 등가회로 분석 (Equivalent-Circuit Analysis of Organic Light-Emitting Diodes in $ITO/TPD/Alq_3/Al$)

  • 안준호;오용철;홍진웅;이준웅;송민종;김태완
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.188-191
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    • 2004
  • We have investigated equivalent-circuit analysis of organic light-emitting diodes in $ITO/TPD/Alq_3/Al$. Complex impedance Z of the device was measured in the frequency range of $40Hz{\sim}1MHz$. We are able to interpret the frequency-dependent response in terms of equivalent-circuit model of contact resistance $R_s$ in series with two parallel combination of $R_{TPD},\;C_{TPD}\;and\;R_{Alq3},\;C_{Alq3}$.

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Integrated Gate Driver Circuit Using a-Si TFT with AC-Driven Dual Pull-down Structure

  • Jang, Yong-Ho;Yoon, Soo-Young;Kim, Binn;Chun, Min-Doo;Cho, Hyung-Nyuck;Cho, Nam-Wook;Sohn, Choong-Yong;Jo, Sung-Hak;Choi, Seung-Chan;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.944-947
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    • 2005
  • Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.

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Self-blast형 $SF_6$ 가스 차단기의 노즐용삭 분석 (Analysis on the Mass Loss in Self-blast type $SF_6$ Gas Circuit Breaker)

  • 정영우;배채윤;안희섭;최종웅;오일성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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    • pp.1422-1423
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    • 2006
  • In our study, the PTFE nozzle ablation in the high-voltage self-blast type $SF_6$ gas circuit breaker was investigated. The test circuit breaker has the structure that the pin electrode is moving and the pressure reservoir volume and the dimension is almost same as commercial 145kv 40kA circuit breaker for similar result in real circuit breaker. The variation of current and arcing time was the range of $36kA_{rms}$(symmetry) - $40kA_{rms}$(asymmetry) and 10-16 ms. From the measured data the tendecy of the mass loss of the nozzle to current load and arc energy was estimated. In this process, the distance from the arc to nozzle(PTFE) surface, area which was exposed to arc and stroke contour was considered. These results will be used to enhance the accuracy of the computational fluid dynamics analysis in circuit breaker and estimate the residual life time of a circuit breaker.

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직선으로 둘러싸인 영역과 비평면적 표면 상에서의 회로 분할과 배치를 위한 그래프 매칭 알고리즘 (A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface)

  • 박인철;경종민
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.529-532
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    • 1988
  • This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

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QFP 패키지의 새로운 고주파 등가 회로 모델 (New High-Frequency Equivalent Circuit Model for QFP Package)

  • 김성종;송상헌
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제54권7호
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    • pp.339-342
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    • 2005
  • We present a new high-frequency equivalent circuit model for 52pin QFP used in typical IC's and extract R, L, and C values of this circuit model using a 3-D E & M field simulator. Futhermore, L and C value variations as a function of Pin number due to the shape differences of the leads have been fitted to 2nd order polynomials in order to extend the applicability of this model.