• Journal of the Korean Institute of Telematics and Electronics
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• v.3 no.2
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• pp.10-17
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• 1966

A method by which solutions of the differential equations of any other distributed circuits can be obtained is described when the solution of the differential equation of an R-C distributed amplifier is known. A graphical method of transforming any R-C ditributed circuit into an equivalent circuit which has a constant R(x)$cdot$C(x) was also obtained. The theoretical verification of this method is possible. For simplicity, any R-C distributed circuit can be transformed into an equivalent circuit which is a distributed circuit of either constant R(x) or C(x). Using this equivalent circuit and considering a lumped circuit, an approximate analysis and synthesis can be made simply.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.17-22
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• 2010

Generally, there are Chua's Circuit, Lorenz Circuit and Duffing circuit in the chaos circuit. Among these chaos circuits, Chua's circuit is well known to make the electronic parts easily. Chua's circuit is the constitute of the linearelements. These are constitute of Resistor component(R), inductor component(L), capacitor(C), and nonlinear element which is constitute of nonlinear resistor. However, L element have a difficult problem to implement real hardware by using commercial parts. Due to this, it has a saturation characteristic. In this paper, we analyzed the simplified Chua's circuit which is replace L to C by PSPICE program. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also confirm this analysis as the result.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.1 no.2
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• pp.57-61
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• 1987

The characteristis of all the instruments and materials used in atomic industry are changed due to irradiation damages by the effects of radiation activities. In this study when R-C series-parallel circuits are irradiated by $\gamma$-ray, variations in its electrical properties have been investigated. The following results are obtained. 1) In the R-C series circuit, the impedance variation ratio is increased as the irradiation quantity is increased up to $10^6[r]$, and above $10^6[r]$, the impedance variation ratio reached at the saturated condition. In the saturated condition, the increasing value was about 1.25 (%). 2) In the R-C series circuit, the power factor variation ratio is decreased as the irradiation quantity is in creased up to $10^6[r]$, and above $10^6[r]$, the power factor variation ratio reached at the saturated condition. In the saturated condition, the decreasing value was about 0.5(%). 3) In the R-C parallel circuit, the impedance variation ratio is increased as the irradiation quentity is increased up to $10^6[r]$, and above $10^6[r]$, the impedance variation reached at the saturated condition. In the saturated condition, the increasing value was about 0.5.(%). 4) In the R-C parallel circuit, the power factor variation ratio is decreased as the irradiation quantity is increased up to $10^6$[r], and above $10^6$[r], the power factor variation ratio reached at the saturated condition. In the saturated condition, the decreasing value was about 1.3(%).

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.8
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• pp.475-481
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• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• Proceedings of the KIEE Conference
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• 2001.11b
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• pp.340-343
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• 2001

In an electrical network, electrical power are transmitted by a various of protection, isolation and control electric circuit devices. This thesis deals with the protection function between circuit-breakers. The protective coordination concerns the behaviour of two devices placed in series in an electrical network, with a short-circuit downstream circuit-breaker. It has two basic principles: First, discrimination which is an increasing requirement of low voltage electrical distribution systems. Second, which is less well known: cascading, which consists of installing a device, whose breaking capacity is less than the three-phase short-circuit current at its terminals and helped by main circuit-breaker. The important advantage of cascading is to be able to install at a branch circuit-breaker of a lesser performance without endangering the safety of the installation for more economical usage. To determine and guarantee co-ordination between two circuit breakers, it is necessary to carry out a theoretical approach, first, and then confirm the results by means of standard tests. This is illustrated in appendix A of IEC 947-2.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.188-191
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• 2004

We have investigated equivalent-circuit analysis of organic light-emitting diodes in $ITO/TPD/Alq_3/Al$. Complex impedance Z of the device was measured in the frequency range of $40Hz{\sim}1MHz$. We are able to interpret the frequency-dependent response in terms of equivalent-circuit model of contact resistance $R_s$ in series with two parallel combination of $R_{TPD},\;C_{TPD}\;and\;R_{Alq3},\;C_{Alq3}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.944-947
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• 2005

Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1422-1423
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• 2006

In our study, the PTFE nozzle ablation in the high-voltage self-blast type $SF_6$ gas circuit breaker was investigated. The test circuit breaker has the structure that the pin electrode is moving and the pressure reservoir volume and the dimension is almost same as commercial 145kv 40kA circuit breaker for similar result in real circuit breaker. The variation of current and arcing time was the range of $36kA_{rms}$(symmetry) - $40kA_{rms}$(asymmetry) and 10-16 ms. From the measured data the tendecy of the mass loss of the nozzle to current load and arc energy was estimated. In this process, the distance from the arc to nozzle(PTFE) surface, area which was exposed to arc and stroke contour was considered. These results will be used to enhance the accuracy of the computational fluid dynamics analysis in circuit breaker and estimate the residual life time of a circuit breaker.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.339-342
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• 2005

We present a new high-frequency equivalent circuit model for 52pin QFP used in typical IC's and extract R, L, and C values of this circuit model using a 3-D E & M field simulator. Futhermore, L and C value variations as a function of Pin number due to the shape differences of the leads have been fitted to 2nd order polynomials in order to extend the applicability of this model.