• Journal of Communications and Networks
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• 제15권2호
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• pp.217-221
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• 2013

Quantum low-density parity-check (LDPC) codes based on the Calderbank-Shor-Steane construction have low encoding and decoding complexity. The sum-product algorithm(SPA) can be used to decode quantum LDPC codes; however, the decoding performance may be significantly decreased by the many four-cycles required by this type of quantum codes. All four-cycles can be eliminated using the entanglement-assisted formalism with maximally entangled states (ebits). The proposed entanglement-assisted quantum error-correcting code based on Euclidean geometry outperform differently structured quantum codes. However, the large number of ebits required to construct the entanglement-assisted formalism is a substantial obstacle to practical application. In this paper, we propose a novel class of entanglement-assisted quantum LDPC codes constructed using classical Euclidean geometry LDPC codes. Notably, the new codes require one copy of the ebit. Furthermore, we propose a construction scheme for a corresponding zigzag matrix and show that the algebraic structure of the codes could easily be expanded. A large class of quantum codes with various code lengths and code rates can be constructed. Our methods significantly improve the possibility of practical implementation of quantum error-correcting codes. Simulation results show that the entanglement-assisted quantum LDPC codes described in this study perform very well over a depolarizing channel with iterative decoding based on the SPA and that these codes outperform other quantum codes based on Euclidean geometries.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.221-225
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• 1994

We described the impact ionization rates of electron in GaAs/AlGaAs MQH(multi- quantum well) using EMC(ensenble Monte Carlo) simulation. Hot electron energy of injected into quantum well is increasing nearly liearly due to the applied electric field to the barrier of MQM inspite of various Al mole fraction in AlGaAs or barrier width. Impact ionization rates are decreasing exponentially by increasing Al mole fraction, and they have peak vague due to the barrier width.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.1-9
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• 2006

We introduce our in-house program, NANOCAD, for the modeling and simulation of carrier transport in nanoscale MOSFET devices including quantum-mechanical effects, which implements two kinds of modeling approaches: the top-down approach based on the macroscopic quantum correction model and the bottom-up approach based on the microscopic non-equilibrium Green’s function formalism. We briefly review these two approaches and show their applications to the nanoscale bulk MOSFET device and silicon nanowire transistor, respectively.

• Current Optics and Photonics
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• 제5권4호
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• pp.375-383
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• 2021

We present a simulation method to design antireflection coating (ARCs) for fiber-coupled superconducting nanowire single-photon detectors. Using a finite-element method, the absorptance of the nanowire is calculated for a defined unit-cell structure consisting of a fiber, ARC layer, nanowire absorber, distributed Bragg reflector (DBR) mirror, and air gap. We develop a method to evaluate the uncertainty in absorptance due to the uncontrollable parameter of air-gap distance. The validity of the simulation method is tested by comparison to an experimental realization for a case of single-layer ARC, which results in good agreement. We show finally a double-layer ARC design optimized for a system detection efficiency of higher than 95%, with a reduced uncertainty due to the air-gap distance.

• 대한전자공학회논문지SD
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• 제41권6호
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• pp.1-7
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• 2004

본 논문에서는 2차원 양자 역학적 모델링 및 시뮬레이션(quantum mechanical modeling and simulation)으로써, 자기정렬 이중게이츠 구조(self-aligned double-gate structure)인 FinFET에 관하여 결합된 푸아송-슈뢰딩거 방정식(coupled Poisson and Schrodinger equations)를 셀프-컨시스턴트(self-consistent)한 방법으로 해석하는 수치적 모델을 제안한다. 시뮬레이션은 게이트 길이(Lg)를 10에서 80nm까지, 실리콘 핀 두께($T_{fin}$)를 10에서 40nm까지 변화시켜가며 시행되었다. 시뮬레이션의 검증을 위한 전류-전압 특성을 실험 결과값과 비교하였으며, 문턱 전압 이하 기울기(subthreshold swing), 문턱 전압 롤-오프(thresholdvoltage roll-off), 그리고 드레인 유기 장벽 감소(drain induced barrier lowering, DIBL)과 같은 파라미터를 추출함으로써 단채널 효과를 줄이기 위한 소자 최적화를 시행하였다. 또한, 고전적 방법과 양자 역학적 방법의 시뮬레이션 결과를 비교함으로써,양자 역학적 해석의 필요성을 확인하였다. 본 연구를 통해서, FinFET과 같은 구조가 단채널 효과를 줄이는데 이상적이며, 나노-스케일 소자 구조를 해석함에 있어 양자 역학적 시뮬레이션이 필수적임을 알 수 있었다.

• 방사선산업학회지
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• 제6권1호
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2009년도 Korea Superconductivity Society Meeting 2009
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• pp.44-44
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• 2009

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 2005년도 춘계학술발표회
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• pp.455-456
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• 2005

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 2005년도 춘계학술발표회
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• pp.117-118
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• 2005

• 한국초전도ㆍ저온공학회논문지
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• 제4권2호
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• pp.11-15
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• 2002

High speed probe for measurement of sin91e flux quantum circuits is comprised of coaxial cables and microstrip lines in order to carry high speed signals without loss. For the impedance matching between coaxial cable and microstrip line, we have determined the dimension of the microstrip line with 50${\Omega}$ impedance by simulation and then have investigated the effect of line width and cross-sectional shape of signal line, dielectric material, thickness of soldering lead at the coaxial-to-microstrip transition Point, and the an91c between dielectric material and end part of the signal line on the characteristics of signal transmission of the microstrip line. From the simulation, we have found that these all parameter's had influenced on the characteristic of signal transmission on the microstrip line and should be reflected in fabricating high speed probe, We have also determined the dimension of coplanar waveguide to fabricate testing sample for performance test of high speed probe.