A design of BIST/BICS circuits for detection of fault and defect and their locations in VLSI memories (고집적 메모리의 고장 및 결함 위치검출 가능한 BIST/BICS 회로의 설계)
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- The Journal of Korean Institute of Communications and Information Sciences
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- v.22 no.10
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- pp.2123-2135
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- 1997