• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.529-530
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• 2008

The proposed CMOS Quadrature VCO for WLAN application was designed in TSMC $0.18\;{\mu}m$ RF CMOS technology. The QVCO based on NMOS back-gate as a coupling transistor and switched capacitors array without tail transistors is designed to generate quadrature output signals. The simulated results show that the QVCO core consumed 3.67 mA and 6.6 mW from a 1.8 V supply. The QVCO is tunable between $4.76\;GHz\;{\sim}\;6.35\;GHz$ and has a phase noise lower than -116.8 ㏈c/Hz at 1 MHz offset over the entire tuning range

• 한국전자파학회논문지
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• 제28권12호
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• pp.941-947
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• 2017

본 논문에서는 $0.35{\mu}m$ CMOS 공정으로 FRS 대역 무전기용 반송파 신호를 쿼드러쳐(Quadrature) 형식으로 출력하는 Fractional-N 위상 고정루프(PLL) 주파수 합성기를 설계 및 제작하였다. 설계한 주파수 합성기의 주요 블록은 전압 제어 발진기(VCO), 전하 펌프(CP), 루프 필터(LF), 위상 주파수 검출기(PFD) 그리고 주파수 분주기이다. VCO는 우수한 위상잡음과 전력 특성을 얻을 수 있는 LC 공진 방식으로 설계했고, CP는 참조 주파수에 따라 펌핑 전류를 조절할 수 있도록 설계하였다. 주파수 분주기는 16분주의 전치 분주기와 3차 델타-시그마 모듈레이터($3^{rd}$ DSM) 방식의 Fractional-N 분주기로 설계하였다. LF는 외부의 3차 RC 루프 필터로 구성하였다. 측정결과, 주파수 합성기의 동작 주파수 영역은 최소 460 MHz에서 최대 510 MHz이고, 출력전력으로는 약 -3.86 dBm을 얻었다. 출력의 위상잡음은 100 Hz offset 주파수에서 -94.8 dBc/Hz이며 위상 루프 고착 시간은 약 $300{\mu}s$이다.

• International Journal of Internet, Broadcasting and Communication
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• 제15권3호
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 하계종합학술발표회논문초록집
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• pp.331-331
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• 2004

• International journal of advanced smart convergence
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• 제10권3호
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.2064-2066
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• 2004

본 논문에서는 새로운 개념인 능동 고조파 결합을 이용한 4위상 전압제어 발진기를 설계, 제작하였다. 4위상 출력 특성을 얻기 위하여 각각의 차동 VCO의 가상 접지(Virtual Ground)면을 본 논문에 제시된 능동 고조파 결합 회로(Active super harmonic coupling)을 이용하여 결합시키는 방법을 적용하였다. 제안된 구조는 다음과 같은 장점을 가지고 있다. 결합구조를 갖는 트랜지스터에 부가적인 전류소비를 줄일 수 있으며, layout상에서 문제되었던 대칭구조를 개선할 수 있다. 또한 기존에 발표되었던 방법인 passive transformer를 이용한 고조파 결합 보다 회로 크기를 줄일 수 있다. 측정결과 출력 전력 -12dBm, -117dBc/Hz @1-MHz 이하의 위상잡음 특성, 2.66GHz${\sim}$2.91GHz의 250 MHz 주파수 가변, 25dB이하의 2차고조파 억압, 7 mA 의 전류 소모(buffer amp. 포함되지 않음)를 가졌다.

• International Journal of Ocean System Engineering
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• 제1권4호
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• pp.205-210
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• 2011

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

• Journal of electromagnetic engineering and science
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• 제10권1호
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• 센서학회지
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• 제28권2호
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.