• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.681-689
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• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1156-1163
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• 2006

This paper presents an ultra wideband(UWB) direct conversion mixer for IEEE 802.15.3a applications with simulation and measurement results. Since the direct conversion mixing causes dc-offset and even-order distortion, the proposed mixer adopts an anti-parallel diode pairs(APDPs) to solve these problems. The proposed mixer consists of an in-phase wilkinson power divider over $3.1{\sim}4.8GHz$, a wideband $45^{\circ}$ power divider over $1.5{\sim}2.4GHz$, and miniatured band pass filters(BPFs) for RF-LO isolations. The conversion loss is optimized with impedance matchings between APDPs and wideband components. The measured mixer shows the conversion loss of 13.5 dB, input third-order intercept-point($IIP_3$) of 7 dBm, and 1-dB gam compression point($P_{1dB}$) of -4 dBm. Quadrature(I/Q) outputs have the magnitude difference of about 1 dB and phase difference of ${\pm}3^{\circ}$.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1063-1066
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• 2000

ln this paper, a new active phase shifter is proposed using a vector sum method, and it is shown that the proposed phase shifter is more efficient than the others in size, power, number of circuits, and gain. Also a unique digital phase control method of the circuit is suggested. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line 3dB quadrature hybrid coupler and variable gain amplifiers (VGAs) using dual gate FETs (DGFETs). Furthermore, it is also shown that the proposed scheme is more efficient and works properly with the digital phase control method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• International Journal of Ocean System Engineering
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• v.1 no.4
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• pp.205-210
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• 2011

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.66-73
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• 2010

This paper proposes the frequency multiplier using diplexer based on CRLH transmission line with dualband characteristic. The diplexer is separated the output signals of harmonic generator, which is generated the harmonic signals using nonlinear device. The diplexer consists of the inphase power divider, 0o/90o phase controller and dual-band quadrature hybrid coupler. This send out the selecting output signals of the harmonic signals and suppresses out of signals. To validate a function of multiplier, the harmonic generator and diplexer with 2 GHz and 3 GHz operating frequency range is implemented. As a result, the proposed frequency multiplier is operated normally.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.844-847
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• 2012

By using LHTL(Left-Handed Transmission Line) which is a form of a metamaterial and conventional RHTL (Right-Handed Transmission Line), we designed, fabricated and tested a broadband $90^{\circ}$ coupler which is a basic circuit for I-Q vector signal generation. Synthetic LHTL and RHTL were implemented with capacitors and inductors only, that the size is minimized. Also, by implementing a Wilkinson power divider which is required for the suggested circuit using a synthetic RHTL, the size of whole circuit is only $11mm{\times}12mm$. For the frequency range 0.8~1.25 GHz, the phase difference at the outputs maintained $90^{\circ}{\pm}5^{\circ}$ and thus, a broadband $90^{\circ}$ coupler could be made in a compact form. for the same frequency range, the insertion loss is less than 1.6 dB and return loss is more than 10.1 dB. To the best of our knowledge, this is the smallest and broadband $90^{\circ}$ coupler for the frequency range and if the circuit is made with MMIC(Monolithic Microwave Integrated Circuit) technology, the size will be reduced much further.