• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.50-57
• /
• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.13-21
• /
• 2010

A energy efficient $V_{pp}$ generator using a variable pumping frequency for mobile DRAM is presented in this paper. The proposed $V_{pp}$ generator exploits 3 stages of a cross-coupled charge pump for energy efficiency. Instead of using a fixed pumping frequency in the conventional $V_{pp}$ generator, our proposed $V_{pp}$ generator adopts a voltage-controlled oscillator and uses variable frequencies to reduce the ramp-up time. As a result, our $V_{pp}$ generator generates 3.0 V output voltage with 24.0-${\mu}s$ ramp-up time at 2 mA current load and 1 nF capacitor load with 1.2 V supply voltage. Experimental results show that the proposed $V_{pp}$ generator consumes around 26% less energy (1573 nJ $\rightarrow$ 1162 nJ) and reduces 29% less ramp-up time (33.7-${\mu}s$ $\rightarrow$ 24.0-${\mu}s$) compared to the conventional approach.

• Progress in Superconductivity and Cryogenics
• /
• v.24 no.1
• /
• pp.23-28
• /
• 2022

A sorption cooler, which utilizes helium-4 as a working fluid, was previously developed and tested in KAIST. The cooler consists of a sorption pump and a thermosyphon. The developed sorption cooler aims to pre-cool a certain amount of the magnetic refrigerant of an adiabatic demagnetization refrigerator (ADR) from 4.5 K to 2.5 K. To simulate the high heat capacitance of the magnetic refrigerant, liquid helium was utilized not only as a refrigerant for the sorption cooling but also as a thermal capacitor. The previous experiment, however, showed that the lowest temperature of 2.7 K which was slightly higher than the target temperature (2.5 K) was achieved due to the radiation heat leak. This excessive heat leak would not occur when the sorption cooler is completely integrated with the ADR. Thus, based on the experimentally obtained pumping speed, the prediction model for the sorption cooler is developed in this study. The presented model in this paper assumes the sorption cooler is integrated with the ADR and the heat leak is negligible. The model predicts the amount of the liquid helium and the required time for the sorption cooling process. Furthermore, it is confirmed that the performance of the sorption cooler is enhanced by reducing the volume of the thermosiphon. The detailed results and discussions are summarized.

• Journal of the Korean Vacuum Society
• /
• v.22 no.3
• /
• pp.168-173
• /
• 2013

In this paper, we would like to introduce Electron Relay Enhancer (ERE), a supplementary device, which improves commercial solar cell efficiency minimizing electron-hole recombination of solar cell. The ERE in this study is mainly composed of two capacitors which are connected to AC power source and bridge diode system which controls electron flow direction. Two capacitors repeat collecting electrons from solar cell and pumping the collected electrons to load resistance or inverter through the bridge diode system. While one positively charged capacitor collect electrons, the other negatively charged one pumps electrons. A positively charged capacitor pulls the more exited electrons from the solar cell, before the exited electrons recombine the holes in solar cell. That is why the ERE system enhances solar cell efficiency. As a result, the measured power increase of the solar cell with the ERE is varied from 5.9 W to 25.6 W in each experimental condition. Maximal increase rate of the solar cell power with ERE is 30.8% of solar cell power without ERE.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.2
• /
• pp.144-151
• /
• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.1-8
• /
• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.