• Nuclear Engineering and Technology
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• v.36 no.4
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• pp.357-363
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• 2004

A prototype long pulse ion source was developed, and the beam extraction experiments of the ion source were carried out at the Neutral Beam Test Stand (NBTS) of the Korea Superconducting Tokamak Advanced Research (KSTAR). The ion source consists of a magnetic bucket plasma generator, with multi-pole cusp fields, and a set of tetrode accelerators with circular apertures. Design requirements for the ion source were a 120kV/65A deuterium beam and a 300 s pulse length. Arc discharges of the plasma generator were controlled by using the emission-limited mode, in turn controlled by the applied heating voltage of the cathode filaments. Stable and efficient arc plasmas with a maximum arc power of 100 kW were produced using the constant power mode operation of an arc power supply. A maximum ion density of $8.3{\times}10^{11}\;cm^{-3}$ was obtained by using electrostatic probes, and an optimum arc efficiency of 0.46 A/kW was estimated. The accelerating and decelerating voltages were applied repeatedly, using the re-triggering mode operation of the high voltage switches during a beam pulse, when beam disruptions occurred. The decelerating voltage was always applied prior to the accelerating voltage, to suppress effectively the back-streaming electrons produced at the time of an initial beam formation, by the pre-programmed fast-switch control system. A maximum beam power of 0.9 MW (i.e. $70\;kV{\times}12.5\;A$) with hydrogen was measured for a pulse duration of 0.8 s. Optimum beam perveance, deduced from the ratio of the gradient grid current to the total beam current, was $0.7\;{\mu}perv$. Stable beams for a long pulse duration of $5{\sim}10\;s$ were tested at low accelerating voltages.

• Korean Journal of Optics and Photonics
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• v.5 no.4
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• pp.466-472
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• 1994

An Argon laser pumped Ti:Sapphire laser has been constructed and self-mode locked. Mode-locking was initiated by a moving mirror mounted on the ball slider and maintained by the self-focusing in the laser crystal and an aperture inside the resonator. A prism pair was used to reduce group velocity dispersion. The bandwidth and the pulse width of the mode-locked pulse were 11 nm, $1000\pm20fs$, respectively. ively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.289-295
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• 2008

In this paper, we designed the off-line PWM(Pulse width modulation) control IC for flyback type power converter to reduce the standby power consumption. In normal state, this off-line PWM IC generates the output pulse with $40\sim60kHz$ frequency and duty ratio of $20\sim88%$. When SMPS operates in standby mode, this IC generates the output pulse with 33kHz frequency and duty ratio of 1 %. SPICE simulation was performed to verify the standby power consumption of the power converter with designed of-line PWM IC. Power converter with designed off-line PWM IC consumes less than 0.3W when it operates in standby mode condition.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.203-204
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• 2006

We present and demonstrate a novel method of alternate-phase return-to-zero (RZ) signal generation and pulse-amplitude equalization simultaneously in a rational harmonic mode-locked fiber ring laser, using a dual-drive Mach-Zehnder (MZ) modulator. By adjusting the voltages applied to both arms of the modulator, the rational harmonic mode-locked pulse trains are equalized in their amplitudes. In addition to that, the amplitude-equalized pulse trains multiplying the repetition rate at ${\sim}10\;GHz$ have alternate $\pi$ phase difference between adjacent pulses. The alternate-phase RZ signal generated by the proposed method enhances transmission performance through the single-mode fiber (SMF) links without dispersion compensation.

• Current Optics and Photonics
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• v.7 no.5
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• pp.557-561
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• 2023

Ultralow-noise soliton pulse generation over a wider Fourier frequency range is highly desirable for many high-precision applications. Here, we realize a low-phase-noise soliton pulse generation by transferring the low phase noise of a mode-locked laser to a silica microcomb. A 21.956-GHz and a 9.9167-GHz Kerr soliton combs are synchronized to a 2-GHz and a 2.5-GHz mode-locked laser through a fractional optoelectronic phase-locked loop, respectively. The phase noise of the microcomb was suppressed by up to ~40 dB at 1-Hz Fourier frequency. This result provides a simple method for low-phase-noise soliton pulse generation, thereby facilitating extensive applications.

• Journal of IKEEE
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• v.15 no.2
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• pp.134-142
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• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.411-414
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• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• ETRI Journal
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• v.33 no.5
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• pp.679-688
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• 2011

A new discrete-amplitude pulse width modulation (DAPWM) scheme for a high-efficiency linear power amplifier is proposed. A radio frequency (RF) input signal is divided into an envelope and a phase modulated carrier. The low-frequency envelope is modulated so that it can be represented by a pulse whose area is proportional to its amplitude. The modulated pulse has at least two different pulse amplitude levels in order that the duty ratios of the pulse are kept large for small input. Then, an RF pulse train is generated by mixing the modulated envelope with the phase modulated carrier. The RF pulse train is amplified by a switching-mode power amplifier, and the original RF input signal is restored by a band pass filter. Because duty ratios of the RF pulse train are kept large in spite of a small input envelope, the DAPWM technique can reduce loss from harmonic components. Furthermore, it reduces filtering efforts required to suppress harmonic components. Simulations show that the overall efficiency of the pulsed power amplifier with DAPWM is about 60.3% for a mobile WiMax signal. This is approximately a 73% increase compared to a pulsed power amplifier with PWM.

• Proceedings of the Optical Society of Korea Conference
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• 2008.02a
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• pp.335-336
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• 2008

We observe the distortion of the back scattered Stokes pulse and the complementary distortion of the transmitted pulse by the stimulated Brillouin scattering when a Q-switched Nd:YAG laser pulse injected into a single mode optical fiber. We determine the constant required energy for the SBS by comparing their temporal shapes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.