• Title/Summary/Keyword: Pulse Power Supply

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철도 급전시스템에서의 고조파 해석 및 대책 연구 (A Study on the Countermeasures to Suppress Harmonics in the Traction Power Supply System)

  • 오광해;이장무;창상훈;한문섭;김길상
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 1999년도 추계학술대회 논문집
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    • pp.318-325
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    • 1999
  • Modern AC electric car has PWM(Pulse Width Modulation)-controlled converters, which give rise to higher harmonics. The current harmonics injected from AC electric car is propagated through power feeding circuit, As the feeding circuit is a distributed constant circuit composed of RLC, the capacitance of the feeding circuit and the inductance on the side of power system cause a parallel resonance and a magnification of current harmonics at a specific frequency. The magnified current harmonics usually brings about various problems. That is, the current harmonics makes interference in the adjacent lines of communications and the railway signalling system. Furthermore, in case it flows on the side of power system, not only overheating and vibration at the power capacitors but also wrong operation at the protective devices can occur. Therefore, the exact assessment of the harmonic current flow must be undertaken at design and planning stage for the electric traction systems. From these point of view, this study presents an approach to model and to analyse traction power feeding system focused on the amplification of harmonic current The proposed algorithm is applied to a standard AT(Auto-transformer)-fed test system in which electric car with PWM-controlled converters is running.

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PFM/PWM 듀얼 모드 피드백 기반 LED BLU 구동용 LLC 공진 변환 제어 IC 설계 (A Design of PFM/PWM Dual Mode Feedback Based LLC Resonant Converter Controller IC for LED BLU)

  • 유창재;김홍진;박영준;이강윤
    • 전기전자학회논문지
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    • 제17권3호
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    • pp.267-274
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    • 2013
  • 본 논문은 Pulse Frequency Modulation(PFM)/Pulse Width Modulation(PWM) 듀얼 모드 피드백 기반 LED 백라이트 유닛 구동용 LLC 공진 변환 제어 IC 설계에 대한 내용을 제시한다. 공진형 변환기에서 하나의 변압기를 사용하면서, 두 가지 출력 전압을 생성할 수 있는 구조를 제안하였으며, Master 출력은 PFM 방식으로 Slave 출력은 PWM 방식으로 제어하도록 설계 하였다. 2차 측 Master 출력을 제어하기 위해서 파워 스위치 제어 신호의 주파수를 조절하는 PFM 피드백과 2차 측 Slave 출력을 제어하기 위해서 파워 스위치 제어 신호의 펄스 폭을 조절하는 PWM 피드백 회로를 설계하였다. 설계된 IC는 $0.35{\mu}m$ 2 Poly 3 Metal BCD(Bipolar-CMOS-DMOS) 공정을 이용하여 레이아웃 되었으며, 면적은 $2.3mm{\times}2.2mm$ 이다. 또한, 설계한 칩은 5 V 공급 전압으로부터 26 mA의 전류를 소모하였다.

Switched Reluctance Motors for Electric Drive of Overland Belt Conveyor

  • Ptakh, Gennady K.;Evsin, Nicholas F.;Zvezdunov, D. Alex;Rozhkov, Dmitry V.;Yakovenko, Alexander E.
    • Journal of international Conference on Electrical Machines and Systems
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    • 제3권4호
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    • pp.409-414
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    • 2014
  • The parameters and operating characteristics of the switched reluctance motor (SRM) for the electric drive of the overland belt conveyor CLM-4500 have been presented. The motor power capacity has been equal to 1250 kW, the motor speed - 1000 min-1. SRM power supply has been provided by a three-phase voltage inverter and a 12-pulse rectifier circuit. The group electric drive has been installed on sections number 2 and 3, 3770 m and 3375 m length, respectively, on the areas of "Berezovsky Strip" JSC, a member of the Siberian Coal Energy Company.

Selective Latch Technique을 이용한 고속의 Dual-Modulus Prescaler (A High-Speed Dual-Modulus Prescaler Using Selective Latch Technique)

  • 김세엽;이순섭김수원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.779-782
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    • 1998
  • This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

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유도가열기용 직.병렬 공진 고주파 인버터의 설계 (Design of High Frequency Inverter with Series-parallel Load-Resonant for Induction Heating application)

  • 홍순일;손의식
    • 조명전기설비학회논문지
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    • 제14권6호
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    • pp.12-17
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    • 2000
  • IN induction heating system the high frequency operation allows a rapid response to current fluctuation in the inverter and result in improved welding quality. To work induction heating of nonferrous metals, a welding power supply is need high working frequency and high power. This paper is shown design technique for increasing working frequency in induction heating for welding coppers. A series-parallel resonate inverter consists of H-type bridges, each of whose arms is composed of a combination of two parallel IGBTs. Inverter operating with the fixed frequency is controlled by pulse width modulation (PWM). As switching adapted the Zero-Voltage Switching technique to reduce switching losses the system is high efficiency. The propose inverter has feature which is high efficiency for very wide load variations with a narrow range of duty cycle ratio control and load short circuit capability. Detailed experimental results obtained from a 48[V] output, 500[W] experimental inverter are presented to verify the concept.

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Focus Electrode(FE) type TWTA용 고전압 펄스전원장치 개발 (Development of High Voltage Pulse Power Supply for Focus Electrode(FE) type TWTA test station)

  • 김성철;김동희
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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    • pp.61-63
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    • 2004
  • Focus Electrode(FE) 기능을 갖는 진행파관 증폭기(TWTA)를 구동하기 위하여 고전압 펄스전원 장치가 필요하다. 이 전원장치는 영부터 -5.0 kV TWT 캐소드 고전압 위에서 펄스 출력으로 동작 되어야 한다. 고전압펄스전원장치는 바이어스 전압이 영부터 -1.5 kV 사이를 연속적으로 가변 할 수 있어야 하고, 펄스의 반복 주파수는 CW로 부터 1 kHz 그리고 펄스폭은 $10\;{\mu}s$ 부터 $500\;{\mu}s$로 선택 가능하여야 한다. 그리고 출력펄스의 상승 및 하강 시간은 150 ns 보다 작아야 한다. 턴-온 및 오프의 스윗칭 시간을 만족시키기 위하여 고전압 스위치는 직렬로 연결된 FET 모듈을 사용하였다. 본 논문에서는 이러한 고전압 펄스전원장치의 설계 및 제작원리 그리고 시험결과에 대하여 다루었다.

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PARALLEL-RESONANT CONVERTER WITH ZVS-PWM CONTROL

  • Ninomiya, Tamotsu;Hashimoto, Takayoshi;Tanaka, Hidekazu;Syoyama, Masahito;Tymerski, Richard-P.
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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    • pp.85-90
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    • 1998
  • A parallel-resonant converter with zero-voltage-switching, pulse-width-modulation(ZVS-PWM) control is proposed. Similar to the previously proposed series-resonant counterpart, it has a simple structure and can be controlled at a constant switching frequency using an active-clamp technique. The nearly constant current output characteristic of the parallel-resonant converter lends itself beneficially to precisely controlled constant current power supply applications. An experimental breadboard featured an accuracy of $\pm$1% for an output current of 2A, with an efficiency of 75%.

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전열화학가속 소요기술 및 연구개발현황 (Technology and the R&D Status for Electro_Thermal_Chemical Gun)

  • 김진성;문상규
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1996년도 추계학술대회 논문집
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    • pp.1023-1027
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    • 1996
  • In this paper, the new technology and R&D status is presented, which accelerates the projectile using the electrical energy to overcome the limit of the conventional gun. The ETC (electro_thermal_chemical) gun, one kind of electric guns, seems to be the highly probable candidate as the next generation gun. The high density power supply and the forming and control of the current pulse are required to develop the ETC gun. And, the interior ballistics considered the mechanism of ETC gun must to be studied.

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의료 기기용 10bit, 100Ks/S Successive Approximation A/D Converter 설계 (A Design of 10-bit 100Ks/S Successive Approximation A/D Converter for Biomedical Applications)

  • 김재운;범진욱;임신일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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    • pp.481-482
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    • 2007
  • This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

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출력전압제어가 용이한 비대칭 펄스형 DC 플라즈마 전원장치에 관한 연구 (A Study On The Asymmetry Pulse Type DC Plasma Power Supply With Easiness To Voltage Control)

  • 유성환;추대혁;윤대식;김준석
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2013년도 전력전자학술대회 논문집
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    • pp.147-148
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    • 2013
  • 최근 각 종 산업 분야에서 박막증착 공정의 다양화, 고품질화, 고속화 추세에 대응하기 위하여 고밀도의 대용량 DC 플라즈마 전원장치에 대한 관심이 커지고 있으며, 아울러 DC 플라즈마 전원장치의 고질적인 문제인 아크 방지회로의 중요성이 부각되고 있다. 효율적인 아크 방지 기법의 하나인 비대칭 펄스형 DC플라즈마 전원장치에서는 짧은 기간 동안 (-)전압을 부하에 인가하여 아크에너지를 감소시키는 방법을 사용하고 있으며 이를 위해 매우 부피가 큰 트랜스포머가 사용되고 있다. 본 연구는 펄스형 DC플라즈마 전원장치에서 나타나는 승압효과를 억제하고 전체 효율을 향상시킴과 동시에 상호 인덕턴스가 작은 트랜스포머를 사용하여 부피를 크게 감소시킨 진보된 형태의 비대칭 펄스형 DC 플라즈마 전원장치를 제안한다.

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