• Journal of IKEEE
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• v.20 no.4
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• pp.361-366
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• 2016

This paper presents the ESD protection circuit with improved electrical characteristic and area efficiency. The proposed ESD protection circuit has higher holding voltage and lower trigger voltage characteristics than the 3-Stacking LVTSCR. In addition, it has only two stages and has improved Ron characteristics due to short discharge path of ESD current. We analyzed the electrical characteristics of the proposed ESD protection circuit by TCAD simulator. The proposed ESD protection circuit has a small area of about 35% compared with 3-Stacking LVTSCR, The proposed circuit is designed to have improved latch-up immunity by setting the effective base length of two NPN parasitic bipolar transistors as a variable.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.425-429
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• 2014

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.317-319
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• 2003

This paper describes an adaptive distance relay for double-circuit line protection with mutual impedance and fault resistance. Double-circuit lines have two operating condition; both lines of a double-circuit line are in operation and one line is switched-off and both ends of the line are grounded. For optimal distance protection, the trip region is calculated, which have respect to mutual impedance and fault resistance.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.459-465
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• 2017

In this paper, we introduce the design consideration of the lightning induced transient protection circuit for the indirect lightning strike on the avionics equipment. The lightning induced surge voltage, which is so-called as indirect effects of lightning, may cause a functional failure or physical damage to the electrical and electronic equipment of aircraft. In order to protect the electrical and electronic equipment of aircraft from the indirect effects of lightning, we should analyze the effect of lightning strike on aircraft and consider applying protection design for each avionics device. However, lightning induced transient protection circuits can have unintended consequences because parasitic inductance elements are exist in PCB and TVS diodes. In this paper, we introduce the design method of the protection circuit considering the parasitic inductance of the protection circuit. In addition, we show the result of verification test performed to validate the protection circuits for indirect effects of lightning.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.587-588
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• 2006

This paper presents the new structural zener triggered silicon-controlled rectifier (ZTSCR) electrostatic discharge (ESD) protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. The proposed ZTSCR has the triggering voltage of 4V. In the ESD event, this proposed novel ZTSCR ESD protection device could trigger quickly and provide an effective discharging path.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.288-292
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• 2002

We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5832-5837
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• 2011

In this paper, we designed a thermal shutdown block for LED applications using a 1 ${\mu}m$ CMOS process. The proposed thermal shutdown protection circuit has been designed with a shut-off temperature of $120^{\circ}C$ and a restart temperature of $90^{\circ}C$ which are suitable conditions for LED driver IC. Also, we got SPICE simulation results of the circuit about process variation of the semiconductor fabrication. From simulation data, process variation rate of the proposed circuit are within 7 % which are good results compared with conventional BJT current mirror type circuit. Finally, we confirmed that the thermal shutdown circuit has good thermal protection function within a LED driver IC.

• Journal of IKEEE
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• v.13 no.1
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• pp.19-29
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• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.