• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.80-81
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• 대한전기학회논문지
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• 제38권10호
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• pp.805-810
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• 1989

This paper presents a method for planning reactive power compensation such as shunt capacitors and reacters so as to maintain bus voltage in acceptable range during steady state operation in power system. The algorithm in this paper decomposes the problem into reactive power planning module for the compensation of bus voltage and load flow module for adjusting the error resulted from the linear approximation. A planning technique is based on linear programming to minimize the amount of added reactive power compensation in each case. Transformer tap settings and generator voltages are adjusted to minimize the compensation. The constraints are the operation limits of the control variables and bus voltages. The result of one sample system is presented to confirm the practical use of the proposed algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.190-193
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• 2001

This paper presents a linear programming based Optimal Reactive Power Dispatch (ORPD) problem using modified sensitivity method. The proposed model minimizes the real power losses and improves the voltage profiles in the system with consideration of voltage and reactive power constraints. The method employs modified sensitivity relationships of power systems to establish both the objective function for minimizing the system losses and the system performance sensitivities relating dependent and control variables. The proposed algorithm has been evaluated with the IEEE 6-bus and IEEE 30-bus systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.194-196
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• 2001

This paper presents a hybrid algorithm for solving security constrained OPF in interconnected power systems, which is based on the combined application of evolutionary programming (EP) and sequential quadratic programming (SQP). The objective functions are the minimization of generation fuel costs and system power losses. In OPF considering security, the outages are selected by contingency ranking method. The control variables are the active power of the generating units, the voltage magnitude of the generator, transformer tap settings and SVC setting. The state variables are the bus voltage magnitude, the reactive power of the generating unit, line flows and the tie line flow. The method proposed is applied to the modified IEEE 14buses model system.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• ETRI Journal
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• 제6권4호
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• pp.31-36
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• 1984

This paper presents an efficient method for real power loss minimization and for improvements in voltage profiles. This method is accomplished by optimal control of reactive power in the system. The problem is formulated as an optimization problem, suitable for solution by linear programming technique. After establishing the objective function for minimizing the system losses with the help of linearised sensitivity relationships of control variables, i. e., the transformer tap position, generator terminal voltages and switchable reactive power sources. The linear programming technique is used to determine the optimal adjustments to the above variables, simultaneously satisfying the constraints. The proposed algorithm has been tested on a sample system and the result is presented and discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1984년도 하계학술회의논문집
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• pp.138-139
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• 1984

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• 대한전기학회논문지:전력기술부문A
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• 제53권5호
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• pp.266-274
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• 2004

This paper presents a scheme for the interconnection of dispersed generator systems(DGs) based on load .unbalance and load model in composite distribution systems. Groups of each individual load model consist of residential, industrial, commercial, official and agricultural load. The unbalance is involved with many single-phase line segment. . Voltage profile improvement and system loss minimization by installation of DGs depend greatly on how they are placed and operated in the distribution systems. So, DGs can reduce distribution real power losses and replace large-scale generators if they are placed appropriately in the distribution systems. The main idea of solving fuzzy goal programming is to transform the original objective function and constraints into the equivalent multi-objectives functions with fuzzy sets to evaluate their imprecise nature for the criterion of power loss minimization, the number or total capacity of DGs and the bus voltage deviation, and then solve the problem using genetic algorithm. The method proposed is applied to IEEE 13 bus and 34 bus test systems to demonstrate its effectiveness.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.