• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 하계학술대회
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2019년도 춘계학술대회
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• pp.464-466
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• 2019

원자력 발전소에 사용되는 제어기는 높은 신뢰도를 요구한다. 한국형 디지털 원자력 발전소인 APR1400 (Advanced Power Reactor 1400)을 비롯하여, 과거 많은 원자력 발전소에 FPGA (Field Programmable Gate Array)와 CPLD (Complex Programmable Logic Device, 이하 FPGA로 통칭)가 포함된 제어기가 적용되고 있다. 적용 초기에는 FPGA를 일반적인 IC (Integrated Circuit)처럼 기기검증 및 성능시험으로만 검증을 하였다. 이후 90년대에 들어 FPGA검증에 대한 연구가 시작되면서, FPGA가 칩이 되기 전까지를 소프트웨어로 간주하여 IEEE 1012-2004를 적용하여 소프트웨어 확인 및 검증을 하였다. 현재에는 유럽표준인 IEC 62566을 적용하여 많은 검증을 하고 있다. 이 방법은 현재까지 가장 현명한 방법으로 평가 받고 있다. 이유는 기존의 검증 방법에서 문제가 되었던 SoC (System on Chip)의 특징을 검증하는 방법을 충분히 적용하였기 때문이다. 하지만, IEC 62566은 유럽 표준으로 아직 미국에서는 채택을 하지 않고 있으며, FPGA에 대해서는 IEEE 1012를 적용하는 것을 유지하고 있다. IEEE 1012-2004나 IEC 62566은 기술 표준으로 실무에서는 다양한 방법을 적용하여 기술 표준을 충족시켜서 적용하고 있다. 이 논문에서는 SoC의 검증 방법이 적용된 원자력 안전등급 FPGA에 대한 검증 방법의 절차 및 중요사항에 대해 설명하고자 한다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• 한국통신학회논문지
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• 제32권11C호
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• pp.1102-1110
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• 2007

본 논문에서는 기존의 정진폭 다중 부호 이진 직교 (CAMB: Constant-Amplitude Multi-code Biorthogonal) 변조 이론을 적용한 변복조기를 프로그래밍 가능한 게이트 배열 (FPGA: Field-Programmable Gate Array)을 사용하여 설계하고 시스템 온 칩 (SoC: System on Chip)으로 구현하였다. 이 변복조기는 FPGA을 이용하여 타겟팅 한 후 보드실험을 통해 설계에 대한 충분한 검증을 거쳐 주문형 반도체 (ASIC: Application Specific Integrated Circuit) 칩으로 제작되었다. 이러한 12Mbps급 모뎀의 SoC를 위하여 ARM (Advanced RISC Machine)7TDMI를 사용하였으며 64K바이트 정적 램 (SRAM: Static Random Access Memory)을 내장하였다. 16-비트 PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter) 등 다양한 통신 인터페이스를 지원할 뿐 아니라 ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter)를 포함하고 있어 실제 현장에서 쉽게 활용될 수 있을 것으로 기대된다.

• 전기전자학회논문지
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• 제17권3호
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• pp.241-247
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• 2013

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

• 제어로봇시스템학회논문지
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• 제10권1호
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• pp.73-80
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• 2004

We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• 융합신호처리학회논문지
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• 제9권1호
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• pp.89-97
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• 2008

전동기의 카오스 현상은 실시간 구현에 있어 바람직하지 않은 동특성으로서, 일반적으로 정상상태에서 전동기 속도가 진동을 한다든지 토크가 랜덤하게 변하는 특징이 있다. 본 논문은 카오스 현상을 갖는 영구자석형 동기 전동기의 적응제어기법을 제안한다. 전동기의 계수(parameter)는 어느 범위 안에서 랜덤하게 변화하는 시변특성을 갖는다. 제어기 설계는 우선, 전동기의 비선형 시스템 모델을 공칭 선형시스템 이론을 적용하여 선형화한다. 또한 실시간에서 시스템 계수의 변화로 인해 발생하는 제어오차를 보상하기 위한 보조제어기법을 제안하며 리아푸노브 안정성 이론을 적용하여 그 제어규칙을 산출한다. 컴퓨터 시뮬레이션을 통하여 제안한 제어기법의 타당성 및 신뢰성을 검증하며 기존의 제어기법과 비교 분석하여 성능의 우수성을 입증하였다. 또한 PSoC(Programmable System-on-Chip)기반 구동 드라이브를 포함하는 실시간 전동기의 제어시스템 실험을 통해 실제 적용가능성을 검증한다.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Journal of information and communication convergence engineering
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• 제15권3호
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• pp.151-159
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• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 추계학술발표회논문집(1)
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.