• KIPS Transactions on Computer and Communication Systems
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• v.6 no.9
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• pp.377-384
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• 2017

The performance improvement of a single core processor has reached its limit since the circuit density cannot be increased any longer due to overheating. Therefore, the multicore and manycore architectures have emerged as viable approaches and parallel programming becomes more important. Haskell, a purely functional language, is getting popular in this situation since it naturally supports parallel programming owing to its beneficial features including the implicit parallelism in evaluating expressions and the monadic tools supporting parallel constructs. However, the performance of Haskell parallel programs is strongly influenced by the performance of the run-time system including the garbage collector. Though a memory profiling tool namely GC-tune has been suggested, we need a more systematic way to use this tool. Since GC-tune finds the optimal memory size by executing the target program with all the different possible GC options, the GC-tuning time takes too long. This paper suggests a basic divide-and-conquer method to reduce the number of GC-tune executions by reducing the search area by one-quarter for every searching step. Applying this method to two parallel programs, a maximally independent set and a K-means programs, the memory tuning time is reduced by 7.78 times with accuracy 98% on average.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.305-312
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• 2005

In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.

• The Journal of Korean Institute of Information Technology
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• v.15 no.12
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• pp.157-164
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• 2017

Mobile ECG signal measurement is a technique to measure small signals of several mV, and many studies have been conducted to remove noise including wandering scheme. Removal of the equipotential line noise caused by shaking or movement of the electrode cable is one of the core research contents for the electrocardiogram measurement. In this study, we proposed a modified step-size of combined NLMS(normalized least squares) and DLMS(delayed least squares) adaptive filter to eliminate baseline noise from ECG signals. The proposed method mainly adjusts initial filter step-size to reduce distortion of original ECG signals characteristic after eliminating baseline noise. The modified filter step-size is scaled by filter order size and distortion minimization factor. This method is suitable for portable ECG device with a small processor and less power consumption. This technique also decreases computation time which is essential for real-time filtering. The proposed filter also increase the signal to noise ratio (SNR) compared to conventional NLMS filter.

• Korean Journal of Remote Sensing
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• v.38 no.3
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• pp.251-263
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• 2022

This paper presents an idea of ScanSAR image formation. For image formation of ScanSAR that utilizes the burst mode for raw signal acquisition, most conventional single burst methods essentially require a step of azimuth stitching which contributes to radiometric and phase distortions to some extent. Time-domain cross correlation could replace SPECAN which is most popularly used for ScanSAR processing. The core idea of the proposed method is that it is possible to relieve the necessity of azimuth stitching by an extension of Doppler bandwidth of the reference function to the burst cycle period. Performance of the proposed method was evaluated by applying it to the raw signals acquired by a spaceborne SAR system, and results satisfied all image quality requirements including 3 dB width, peak-to-sidelobe ratio (PSLR), compression ratio,speckle noise, etc. Image quality of ScanSAR is inferior to that of Stripmap in all aspects. However, it is also possible to improve the quality of ScanSAR image competitive to that of Stripmap if focused on a certain parameter while reduced qualities of other parameters. Thus, it is necessary for a ScanSAR processor to offer a great degree of flexibility complying with different requirements for different applications and techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Journal of Space Technology and Applications
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• v.1 no.1
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• pp.33-40
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• 2021

Based on the requirements of a total weight of 42 kg or less, the NEXTSat-2 SAR (synthetic aperture radar) system was developed. As the NEXTSat-2 is a small-sized satellite, the SAR system was designed to account for about 40% of the dry mass of the payload relative to the total mass. Among the major components of the SAR system - which are an antenna, an RF transceiver, a baseband signal processor, and a power unit - a part with a particularly large dry mass is the antenna, the core of the SAR system. Whereas various selections are possible in consideration of gain and efficiency when designing the antenna, the micro-strip patch array antenna was adopted by reflecting the dry mass, power, and resolution required by the NEXTSat-2 project. In order to meet the mission requirement of the NEXTSat-2, the antenna was developed with a frequency of 9.65 GHz, a gain of 42.7 dBi, and a return loss of -15 dB. The performance of the antenna was verified by conducting a field test onboard the vehicle.