• Proceedings of the KIEE Conference
• /
• 2000.07b
• /
• pp.1433-1435
• /
• 2000

Currently KERI is participating a project whose goal is to develop the Korean High-Speed Train(KHST) with maximum speed of 350kph. KERI's responsibility is the electrical system engineering that includes engineering design of an on-board computer system for diagnosis and control of train set and electrical/mechanical devices. A system engineering approach of the design is performed in order to guarantee the passenger safety and economically viable train for on-board control system construction, operation and maintenance. This paper presents the draft engineering des on-board computer system that ensures the s and reliability of KHST. The draft is focuse network interfaced distributed processing system.

• Proceedings of the IEEK Conference
• /
• 2000.11c
• /
• pp.47-50
• /
• 2000

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI , which requires the use of postal 4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state bar code for high speed processing that has been specifically designed for information processing of logistics and automatic processing of the mail items. This paper describes a method of Reed-Solomon encoding for creating error correction codeword of 4-state bar code.

• Journal of IKEEE
• /
• v.21 no.1
• /
• pp.100-103
• /
• 2017

Motion estimation occupies the largest computation in the video compression. Multiple processing elements are often exploited in parallel to meet processing speed. More processing elements increase processing speed, but they also increase hardware area. therefore, it is important to optimize the number of processing element. HEVC (high efficiency video coding) usually exploits multi-stage motion estimation algorithms for low computation and high performance. Since the number and position of search points are different in each stage, the utilization of the processing elements is not always 100% and the utilization is quite different with the number of processing elements. In this paper, the optimizing method is proposed on the number of processing elements. It finds out the optimal number of the processing elements for the given multi-stage motion estimation algorithm by calculating utilization and execution cycle of the processing elements.

• Journal of Information Processing Systems
• /
• v.11 no.2
• /
• pp.266-279
• /
• 2015

In this paper, we propose a novel block cipher mode of operation, which is known as the counter chain (CC) mode. The proposed CC mode integrates the cipher block chaining (CBC) block cipher mode of operation with the counter (CTR) mode in a consistent fashion. In the CC mode, the confidentiality and authenticity of data are assured by the CBC mode, while speed is achieved through the CTR mode. The proposed mode of operation overcomes the parallelization deficiency of the CBC mode and the chaining dependency of the counter mode. Experimental results indicate that the proposed CC mode achieves the encryption speed of the CTR mode, which is exceptionally faster than the encryption speed of the CBC mode. Moreover, our proposed CC mode provides better security over the CBC mode. In summary, the proposed CC block cipher mode of operation takes the advantages of both the Counter mode and the CBC mode, while avoiding their shortcomings.

• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.22-24
• /
• 2004

This paper proposes a printing quality inspection system of film-type envelopment. Since the printing system is running at very high-speed (140m/min.) and the line error has very narrow width, we have to choose one-dimensional high-speed and high-resolution line scan camera. The vibration of the printing machine and the illumination environment make the inspection problem more harder. To obtain reliable inspection results, many software image processing techniques are applied and many parameters are tuned. The performance of the proposed system is proved by many simulations and long time real-plant experiments.

• Journal of Information Processing Systems
• /
• v.14 no.2
• /
• pp.487-498
• /
• 2018

The purpose of the high-speed railway construction is to better satisfy passenger travel demands. Accordingly, the design of the train working plan must also take a full account of the interests of passengers. Aiming at problems, such as the complex transport organization and different speed trains coexisting, combined with the existing research on the train working plan optimization model, the multiobjective bi-level programming model of the high-speed railway passenger train working plan was established. This model considers the interests of passengers as the center and also takes into account the interests of railway transport enterprises. Specifically, passenger travel cost and travel time minimizations are both considered as the objectives of upper-level programming, whereas railway enterprise profit maximization is regarded as the objective of the lower-level programming. The model solution algorithm based on genetic algorithm was proposed. Through an example analysis, the feasibility and rationality of the model and algorithm were proved.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 1991.10a
• /
• pp.45-47
• /
• 1991

In this research, we verify the relations between the mechanical hardness of a strip and the output of Residual Magnetic Flux Detector, which is installed in the end side of #2 CAL. First, we install the strip speed detector and get a hardness signal and a speed signal 2 seconds, and then do signal processing and send an output to a printer every 30 seconds. The system that performs above functions is Magnetic Hardness Data Acquisition & Processing System. We got the relation between output current and hardness for the strip of T3 BP through on-line tests. Seconds, we made a hardness Measurement Simulator and observed the speed characteristics of residual magnetic flux, with using it.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.21 no.48
• /
• pp.145-152
• /
• 1998

Driving performance is characterized by many things such as driver's experience period, age, ability of information processing and reaction time of control devices and so forth. However, each factor of driving performance is needed to help and screen a poor driver for safe driving. In this paper, driving performance was estimated by reaction of manipulating brake, accelerator, steering wheel and speed. Subjects were grouped by experience of accident and age. Combinations of every group were analysed. For all the dependent variables, only steering wheel and speed were shown to have significant difference, which could be regarded as visual information of speed and direction were the important factors to drive safely. Especially for tile elderly, it is needed to enhance their ability of visual information processing that is to be decreased with aging. Therefore driving simulator to train and screen the poor driver should be studied.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.168-176
• /
• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.4C
• /
• pp.379-388
• /
• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.