• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.788-791
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• 2010

본 논문에서는 인쇄공정기술로써 ETRI $0.8{\mu}m$ CMOS 공정을 사용하여 수동형 인쇄 RFID 태그칩용 64bit ROM을 설계하였다. 먼저 태그 칩의 제작단가를 줄이기 위하여 기존 실리콘 기반의 복잡한 리소그래피 공정을 사용하지 않고 게이트 단자인 폴리 층을 프린팅 기법 중 하나인 임프린트 공정을 사용하여 구현하였다. 그리고 �弼壅� ROM 셀 회로는 기존 ROM 셀 회로의 NMOS 트랜지스터대신에 CMOS 트랜스미션 게이트를 사용함으로써 별도의 BL 프리차지 회로와 BL 감지 증폭기가 필요 없이 출력 버퍼만으로 데이터를 읽어낼 수 있도록 하였다. $0.8{\mu}m$ CMOS 공정을 이용하여 설계된 8 행 ${\times}$ 8 열의 어레이를 갖는 64b ROM의 동작전류는 $9.86{\mu}A$이며 레이아웃 면적은 $311.66{\times}490.59{\mu}m^2$이다.

• 한국컴퓨터정보학회논문지
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• 제21권3호
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• pp.1-8
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• 2016

The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets $C_i$, (i=1,2,3), the $C_1$ is assigned to front F, $C_2$ is back B, and $C_3$ is B-F and connected with via. For the various experimental data, though this algorithm can be require O(np) polynomial time, we obtain the optimal solution for all of data.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1195-1196
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• 2008

It is difficult to solve PCB(Printed Circuit Board) Noise problem. Because Electronic circuit system operates very high frequency. Resonance analysis of PCB layout by PI(Power Integrity) Simulation method visualizes distribution of Switching noise between VDD and GND. By using de-cap, we reduce impedance and solve the EMI problems.

• 전기전자학회논문지
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• 제17권3호
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• pp.324-331
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• 2013

본 논문에서는 멤리스터 에뮬레이터 회로를 PCB 보드 상에서 구현하여 이의 측정을 통해서 멤리스터의 고유한 pinched hysteresis 특성을 관찰하였다. PCB 보드 상에서 구현된 멤리스터 에뮬레이션 회로는 간단한 부품으로 구성되어 있고 복잡한 회로 블록을 사용하지 않았기 때문에 집적회로의 구현 시에도 매우 작은 면적으로 설계가 가능하다는 장점이 있다. 또한 본 논문에서는 프로그램 가능한 이득증폭기를 멤리스터 에뮬레이션 회로를 사용하여 설계해서 이 회로의 전압이득이 멤리스터의 저항의 프로그래밍을 통해서 조절이 가능하다는 것을 보였다. 이득증폭기에 사용되는 멤리스터 에뮬레이션 회로의 구현을 위해서 멤리스터 소자의 특성 중에 하나인 threshold switching 특성이 회로로 구현되어 VREF 보다 낮은 전압이 인가되었을 때는 멤리스터의 저항 값이 변하지 않도록 설계하였고 이의 동작을 시뮬레이션을 통해서 검증하였다. 본 논문에서 PCB 보드 상에서 구현되고 검증된 멤리스터 에뮬레이션 회로와 이 회로를 이용한 프로그램 가능한 이득증폭기는 멤리스터 소자의 실제 제작이 불가능한 경우에, 멤리스터의 동작과 기능, 특성 및 멤리스터 응용회로의 이해에 많은 도움이 될 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.577-579
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• 2004

Digital hearing aids enclose $6{\sim}8$ tiny components. Those electromechanical components are individually wired by soldering which is a manual labor and sometimes causes components' damage by heating. This paper suggests a PCB design for overcome these problems. Several PCBs are designed and manufactured and circuited to produce ITE(In The Ear) type hearing aids which are inserted in the ear canal. The most optimal size of the PCB design for the ITE hearing aid is presented in this paper.

• Journal of Power Electronics
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• 제17권2호
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• Journal of Power Electronics
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• 제9권2호
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• pp.308-319
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• 2009

An increasing number of power electronic applications require high power density. Therefore, the switching frequency and switching speed have to be raised considerably. However, the very fast switching transients induce a strong voltage and current ringing. In this work, a novel damping concept is introduced where the parasitic wiring inductances are advantageously magnetically coupled with a damping layer for attenuating these unwanted oscillations. The proposed damping layer can be implemented using standard materials and printed circuit board manufacturing processes. The system behavior is analyzed in detail and design guidelines for a damping layer with optimized RC termination network are given. The effectiveness of the introduced layer is determined by layout parasitics which are calculated by application of the Partial Element Equivalent Circuit (PEEC) simulation method. Finally, simulations and measurements on a laboratory prototype demonstrate the good performance of the proposed damping approach.

• 한국산학기술학회논문지
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• 제19권2호
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• pp.639-643
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• 2018

전자 시스템이 소형화, 이동성의 요구에 따라 전력 변환의 필요성이 계속 증가하고 있다. 또한 전력 변환에는 전력 효율과 함께 전력 변환시스템의 소형화를 위해 적용하는 스위칭에 의한 잡음으로부터 시스템 안정성이 보장되어야 한다. 따라서 전력 변환시 스위칭 잡음을 감소시킬 수 있는 대책이 필수적이다. 본 논문에서는 DC/DC Buck Converter회로를 구성하였고, reference plane을 갖는 4층 PCB 회로 구조에서 부품의 배치를 변경할 경우 발생하는 스위칭 잡음특성을 비교 분석하였다. 또한, Reference Plane을 제거한 양면 PCB회로 구조에서 부품 배치를 달리하였을 경우 스위칭 잡음 특성을 각각 시뮬레이션으로 비교 분석하였다. 그 결과 4층 PCB회로 구조에서는 Current return path에 따라 Radiated Emission 특성이 12dB, Conducted Emission 특성이 7~8dB 감소됨을 확인하였다. 또한 양면 PCB회로 구조에서는 Conducted Emission이 20~25dB 감소됨을 확인하였다. 이로써 전력 변환 회로를 설계할 경우 Current return path의 구성에 따라 잡음 특성을 향상시킬 수 있음을 확인하였다.

• 센서학회지
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• 제17권1호
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• pp.15-22
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• 2008

When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.