• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.405-413
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• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.4
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• pp.3-10
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• 2005

Every cell position of a maximum-length 90/150 cellular automata(CA) generates the same pseudo-noise(PN) sequence corresponding to the characteristic polynomial of the CA with a phase shift. Unlike LFSRs, the phase shift is generally different between stages of a CA. In this paper, we propose an algorithm to compute relative phase shifts between stage of a CA. Our algorithm does not need Shank's algorithm to compute relative phase shifts and does not need any previous phase shifts to compute a phase shift. Moreover it is done in time $O(2^n)$.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.4
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• pp.194-200
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• 2012

In this paper we analyze the code sequence generating algorism defined on $GF(2^n)$ proposed by S.Bostas and V.Kumar[7] and derive the implementation functions of code sequence generator using Boolean functions which can map the vector space $F_2^n$ of all binary vectors of length n, to the finite field with two elements $F_2$. We find the code sequence generating boolean functions based on two kinds of the primitive polynomials of degree, n=5 and n=7 from trace function. We then design and implement the code sequence generators using these functions, and produce two code sequence groups. The two groups have the period 31 and 127 and the magnitudes of out of phase(${\tau}{\neq}0$) autocorrelation and crosscorrelation functions {-9, -1, 7} and {-17, -1, 15}, satisfying the period $L=2^n-1$ and the correlation functions $R_{ij}({\tau})=\{-2^{(n+1)/2}-1,-1,2^{(n+l)/2}-1\}$ respectively. Through these results, we confirm that the code sequence generators using boolean functions are designed and implemented correctly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.438-449
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• 2012

This paper presents new CRC-p codes for VHF band maritime wireless communication system based on performance analysis of various CRC codes. For this purpose, we firstly describe the method of determination of undetected error probability and minimum Hamming distance according to variation of CRC codeword length. By using the fact that the dual code of cyclic Hamming code and primitive BCH code become maximum length codes, we present an algorithm for computation of undetected error probability and minimum Hamming distance where the concept of simple hardware that is consisted of linear feedback shift register is utilized to compute the weight distribution of CRC codes. We also present construction of transmit data frame of VHF band maritime wireless communication system and specification of major communication parameters. Finally, new optimal CRC-p codes are presented based on the simulation results of undetected error probability and minimum Hamming distance using the various generator polynomials of CRC codes, and their performances are evaluated with simulation results of bit error rate based on the Rician maritime channel model and ${\pi}$/4-DQPSK modulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.123-136
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• 2004

In this paper, complexity and regularity of polynomial multiplication over $GF({2^n})$ are defined by using Hamming weight of rows and columns of the matrix ever GF(2) which represents polynomial multiplication. It is shown experimentally that in order to construct the block cipher robust against differential cryptanalysis, polynomial multiplication of substitution layer and the permutation layer should have high complexity and high regularity. With result of the experiment, a way of constituting S box and G function is suggested in the block cipher whose structure is similar to SEED, which is KOREA standard of 128-bit block cipher. S box can be formed with a nonlinear function and an affine transform. Nonlinear function must be strong with differential attack and linear attack, and it consists of an inverse number over $GF({2^8})$ which has neither a fixed pout, whose input and output are the same except 0 and 1, nor an opposite fixed number, whose output is one`s complement of the input. Affine transform can be constituted so that the input/output correlation can be the lowest and there can be no fixed point or opposite fixed point. G function undergoes linear transform with 4 S-box outputs using the matrix of 4${\times}$4 over $GF({2^8})$. The components in the matrix of linear transformation have high complexity and high regularity. Furthermore, G function can be constituted so that MDS(Maximum Distance Separable) code can be formed, SAC(Strict Avalanche Criterion) can be met, and there can be no weak input where a fixed point an opposite fixed point, and output can be two`s complement of input. The primitive polynomials of nonlinear function affine transform and linear transformation are different each other. The S box and G function suggested in this paper can be used as a constituent of the block cipher with high security, in that they are strong with differential attack and linear attack with no weak input and they are excellent at diffusion.