• 한국항행학회논문지
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• 제27권2호
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• pp.197-202
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• 2023

본 논문은 5G 시스템에 적용되어 인 빌딩, 지하철과 터널등에 사용되는 50 Watts급 중계기용 고효율 전력증폭기 설계 방법과 전기적 특성을 나타내었다. 여기서 설계된 전력증폭기의 종단 트랜지스터는 GaN(gallium nitride)을 사용하여 도허티방식으로 구성하였으며, 선형성을 만족시키기 위해서 DPD(digital predistortion)를 이용하여 혼변조 신호를 제거하였다. 또한, 5G 시스템에서 요구되는 증폭기의 이득 제어와 경보 처리등 다양한 요구사항을 처리하기 위해서 마이크로프로세서가 전력증폭기 내부에 존재하게 설계하였다. 통신사업자가 요구하는 규격의 전력증폭기는 46.5 dBm 출력전력과 증폭기 전체의 효율이 37%가 측정되었고, EVM(error vector magnitude)은 2.3% 그리고 ACLR(adjacent channel leakage ratio)은 52.8 dBc로 측정되어 요구되는 전기적 특성과 다양한 경보조건을 만족하는 것을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.377-380
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• 2000

In this paper, a new adaptive linearizer architecture with the predistorter is proposed. In the M.Ghaderi's paper, two analog predistorters and an envelope detector are used. Analog circuits for the analog predistorter and the envelope detector can cause imperfection and inaccuracy of the system and make circuits more complex. To solve those problems, most of processes including the predistortion are made by the DSP. The RLS algorithm is applied so that the errors between power amplifier output signals through the postdistorters and predistorted input signals can be converged to the global minimum.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.77-78
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• 2005

In this paper, Compact Microstrip Resonants Cell(CMRC) have been employed to suppress IMD(Intermodulation Distortion) of the 3-Way Doherty amplifier. This method can not only improve the linearly and the efficiency but also is simpler, smaller and more inexpensive than existing linearly methods; (for example Harmonic feedback, Back off, Feed-forward, Predistortion and so on.) Also, the proposed 3-way Doherty amplifier using only one divider has been reduced size of existing 3-Way Doherty amplifier. As a result, the proposed Doherty amplifier using CMRC and only one divider has been improved for the IMD$_3$ by 4.474dBc, and the PAE by 9.199%, respectively.

• 전자공학회논문지A
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• 제31A권12호
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• pp.9-15
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• 1994

In this paper, the linearized power amplifier using digital adaptive predistorter is implemented in order to restrict spectral spreading and adjacent channel interference. The linearized systems is composed of a DSP56001 processor that executes predistortion in baseband. 90.deg. phase shifter, power splitter/combiner, quadrature modulator/demodulator of 360MHz band, and nonlinear amplifier. A ${\pi}$/4-shift QPSK is used to modulate digital random signals. As the quantized power of baseband signal and the output of amplifier are fed to the predistorter, and predistorting values are calculated using an adaptive algorithm. In the experiment, a peak to sidelobe ratio of the linearized amplifier is improved up to 15dB in comparison with conventional nonlinear amplifier, which means that the distortion of transmitted signal is decreased and adjacent channel interference was reduced.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.182-185
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• 2002

A RE predistorted asymmetric Doherty amplifier for CDMA IS-95 signal has been fabricated using GaAs FETs. The Doherty amplifier used a Class AB main device and a Class C auxiliary device. At 6 ㏈ back-of from Pl ㏈ of 34 ㏈m, PAE of 27% was measured. This Doherty amplifier has higher PAE than Class AB for over 20 dB range of pout power. A RF predistortion linearizer is applied to the Doherty amplifier to improve the IMD cancellation performance. The 3rd order IMD cancellation of 12.2 ㏈ was achieved at output power of 18 ㏈m.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.393-396
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• 2001

In this paper, a new type of linearizer using a parallel diode with a bias feed resistance has been studied. It has positive gain and negative phase deviations because of a nonlinearity of the diode and movement of bias point cause by a voltage drop at the bias feed resistance. This predistortion linearizer consists of the little component and miniaturizes circuit design. The characteristics of this linearizer can be easily tuned using input bias voltage. In fabricated linearizer, maximum gain and Phase deviation of the linearizer is 1dB, 21$^{\circ}$ respectively. By applying its characteristics to the power amplifier, it will be linearized power amplifier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.211-212
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• 2006

This paper represents a Doherty amplifier with analog predistorter to improve the linearity of the Doherty amplifier while preserving the high efficiency. A $3^{rd}$-order predistorter cancels $5^{th}$-order intermodulation (IM5) as well as $3^{rd}$-order intermodulation (IM3) components by their same phase difference in the predistorter and Doherty amplifier. This is accomplished by independently controlling their phase by using the phase-controlled error generator in the predistorter. For experimental verification, a $3^{rd}$-order predistorter has been implemented and tested in a 180-W Doherty amplifier at the wide-band code division multiple access (WCDMA) band. The measured results show good performance with the predistortion Doherty amplifier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• 한국전자파학회논문지
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• 제11권8호
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• pp.1428-1436
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• 2000

이 논문에서는 DSP로 구현하기에 적합한 적응 전치왜곡 선형화기를 제안한다. 기존에 제안된 선형화기와 달리 애널러그 전치왜곡기를 사용하지 않고 DSP로 전치왜곡을 시행한다. 전치왜곡기의 출력신호와 후처리기의 출력신호사이의 오차가 글로벌 최소치에 접근하도록 RLS(recursive least square) 적응 앨거리즘을 적용한다. 제안된 선형화기에 대한 컴퓨터 씨뮬레이션 결과는 좋은 성능을 보인다.

• Journal of electromagnetic engineering and science
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• 제8권1호
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• pp.17-22
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• 2008

It is presented that sampling rates for behavioral modeling of quasi-memory less nonlinear devices can be far less than the Nyquist rate of the input signal. Although it has been believed that the sampling rate of nonlinear device modeling should be at least the Nyquist rate of the output signal, this paper suggests that far less than the Nyquist rate of the input signal can be applied to the modeling of quasi-memoryless nonlinear devices, such as frequency multipliers. To verify, a QPSK signal at 820 MHz were applied to a frequency tripler, whereby the device can be utilized as an up-converting mixer into 2.46 GHz with the aid of digital predistortion. AM-AM, AM-PM and PM-PM can be successfully measured regardless of sampling rates.