• 대한전기학회논문지:시스템및제어부문D
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• 제50권12호
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• pp.590-596
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• 2001

The pre-emphasis is an essential process for speech signal processing. Widely used two methods are the typical method using a fixed value near unity and te optimal method using the autocorrelation ratio of the signal. This study proposes a new pre-emphasis method using the short-term energy difference of speech signal, which can effectively compensate the glottal source characteristics and lip radiation characteristics. Using the proposed pre-emphasis, speech analysis, such as spectrum estimation, formant detection, is performed and the results are compared with those of the conventional two pre-emphasis methods. The speech analysis with 5 single vowels showed that the proposed method enhanced the spectral shapes and gave nearly constant formant frequencies and could escape the overlapping of adjacent two formants. comparison with FFT spectra had verified the above results and showed the accuracy of the proposed method. The computational complexity of the proposed method reduced to about 50% of the optimal method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.691-694
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• 2005

This paper proposed 10Gbps driver with pre-emphasis for high speed transmitter. the proposed driver increase bandwidth using Ft doubler method and design driver block and pre-emphasis block in together. Pre-emphasis functionality confirmed to control VDS of current source o driver, not to control slew rate of termination resistor. The proposed driver is designed in a 1.5V/0.13um 1-poly, 5-metal CMOS mixed-signal process.

• IEIE Transactions on Smart Processing and Computing
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• 제5권3호
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권4호
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

• 한국음향학회지
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• 제38권2호
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• pp.240-245
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• 2019

본 논문은 수중 음향센서 데이터의 원거리 케이블 전송에 관한 연구 결과이다. LVDS(Low Voltage Differential Signaling) 전송 방식으로 설계된 데이터 송수신기의 케이블에 대한 원거리 전송 신호를 측정하고 지터 특성을 분석하였다. 지터 특성을 저감하기 위하여, 원거리 전송에 따라 감쇠될 송신 신호를 역 보상하는 고역 강조(pre-emphasis) 기법을 적용하였으며, 전송 거리에 따라 송신 특성을 검증하였다.

• 한국전자파학회논문지
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• 제13권3호
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• pp.263-268
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• 2002

OFDM(orthogonal frequency division multiplexing) 시스템은 ISI와 주파수 선택적 채널에서 매우 강건한 (robust) 특성을 갖기 때문에 차세대 고속 데이터 전송에 효과적인 기술이다. 그러나, OFDM 시스템에서는 많은 부반송파를 사용하므로 높은 PAPR(peak to averahe power ratio)이 발생된다. 높은 PAPR의 OFDM 신호가 송신단의 비선형 증폭기를 통과할 때 심각한 왜곡이 발생한다. 본 논문에서는 프리엠파스시스 및 클리핑 기법을 이용하여 PAPR를 감소하였다. 이 방법은 IFFT 출력 신호를 프리엠파시스(de-emphasis)시키는 과정을 이용하여 효과적인 성능 개선을 갖는다. 부반송파의 수가 16개, QPSK 변조방식을 사용하고, 프리엠파시스 변화점이 IFFT 출력신호 최대진폭의 3/9이고, IFFT 출력진폭이 11인 지점에서 클립을 할때, CCDF(complementary cumulative density function)확률이 10/녀ㅔ -3/에서 PAPR이 약5.7㏈ 정도이고, BER=$10^{-3}$에서 요구 SNR은 기존의 OFDM보다 약 2 ㏈성능 개선을 보인다.

• 대한전자공학회논문지SD
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• 제46권8호
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• pp.71-78
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• 2009

고속 메모리의 인터페이스를 위한 8 ${\times}$ 8-Gb/s/채널 4-레벨 펄스진폭변조 입출력회로를 1.35V의 공급전압을 가지는 70nm DRAM 공정을 이용하여 설계하였다. 4-레벨 펄스진폭변조를 위한 3 가지의 eye opening에서 상위와 하위 eye의 전압과 시간의 마진을 증가시키기 위해 비균형 4-레벨 펄스진폭변조의 신호전송 기법을 제안한다. 제안한 기법은 수신 단에서의 기준 전압 노이즈 영향을 33% 감소시키며, 이를 통계적인 수식을 통해 분석한다 일반적인 직렬 인터페이스 대비 신호 손실이 적은 DRAM 채널의 ISI(신호간의 간섭)를 줄이기 위해 수신 단에서 단일 비트 펄스의 테스트 신호를 적분함으로 ISI를 측정하는 적응형 프리앰퍼시스 기법을 구현한다. 또한, 이를 위해 정해진 테스트 패턴에 의해 최적의 ISI를 측정하기 위한 적분 클럭의 시간 보정기법을 제안한다.