• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.12
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• pp.590-596
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• 2001

The pre-emphasis is an essential process for speech signal processing. Widely used two methods are the typical method using a fixed value near unity and te optimal method using the autocorrelation ratio of the signal. This study proposes a new pre-emphasis method using the short-term energy difference of speech signal, which can effectively compensate the glottal source characteristics and lip radiation characteristics. Using the proposed pre-emphasis, speech analysis, such as spectrum estimation, formant detection, is performed and the results are compared with those of the conventional two pre-emphasis methods. The speech analysis with 5 single vowels showed that the proposed method enhanced the spectral shapes and gave nearly constant formant frequencies and could escape the overlapping of adjacent two formants. comparison with FFT spectra had verified the above results and showed the accuracy of the proposed method. The computational complexity of the proposed method reduced to about 50% of the optimal method.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.691-694
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• 2005

This paper proposed 10Gbps driver with pre-emphasis for high speed transmitter. the proposed driver increase bandwidth using Ft doubler method and design driver block and pre-emphasis block in together. Pre-emphasis functionality confirmed to control VDS of current source o driver, not to control slew rate of termination resistor. The proposed driver is designed in a 1.5V/0.13um 1-poly, 5-metal CMOS mixed-signal process.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.240-245
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• 2019

This paper is a study result on long distance transmission of underwater acoustic sensor data over cable. The data transceiver is designed using the LVDS (Low Voltage Differential Signaling) transmission scheme, and the jitter characteristics are analyzed by measuring the long distance transmission signal through the cable. In order to reduce the jitter, a pre-emphasis technique is applied to compensate the transmitting signal to be attenuated by long distance transmission, and the transmission characteristics were verified according to the distance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.263-268
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• 2002

DFDM is a good candidate for beyond-3G high-speed wireless communication application because of the robustness to the intersymbol interference and multipath fading. However. an OFDM signal has a serious problem of the high PAPR, which results in the significant nonlinear distortion when it passes through a nonlinear high power amplifier. We propose a new PAPR reduction method using pre-emphasis and clipping. Via the proposed method, the OFDM output signal can have a low PAPR and BER improvement. Then. de-emphasis process is requisite in OFDM receiver. PAPR is reduced to about 5.7 ㏈ at the CCDF= 10$\^$-3/ when the subcarrier number is 16, QPSK modulation is used. pre-emphasis change point Is 3/9 of the peak amplitude of the IFFT output and clipping level is 11 in the IFFT output amplitude. The required SNR at BER=10$\^$-3/ the proposed system is improved by 2 dB than that of the original OFDM system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.71-78
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• 2009

An 8${\times}$8-Gb/s/channel 4-PAM transceiver was designed for high speed memory applications by using 70nm DRAM process with 1.35V supply. An asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margin of upper and lower eyes in 3-class eye opening. A mathematical basis shows that this scheme statistically reduces 33% of reference noise effect in a receiver. Also, an adaptive pre-emphasis scheme, which utilizes a lone-bit pulse with integrator at the receiver, is introduced to reduce ISI for a simple DRAM channel. In this scheme, an integrating clock timing calibration by using a pre-determined pattern is proposed for the optimum ISI measurement.