• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• International Journal of Control, Automation, and Systems
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• v.6 no.5
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• pp.660-669
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• 2008

This paper presents a new carrier based pulse-width modulation (PWM) method for matrix converters. By using the concept of average over one switching period, the modulation algorithm and the required equations are derived to synthesize the desired output voltage and to achieve the controlled input power factor. The proposed method uses a continuous carrier and the predetermined duty ratio signals to directly generate the gating signals and, thus, is referred to as "direct duty ratio PWM (DDPWM)". The feasibility and validity of the proposed method were verified by simulation and experiment.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.12
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• pp.655-660
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• 2003

This paper proposes new single stage power factor correction (PFC) full bridge converter. The proposed converter is combined previous ZVS full bridge DC/DC converter with two inductors, two diodes, two magnetic coupling transformer for PFC. This process of power is isolated from the source and also regulate stable DC output voltage in a category. In this topology, the voltage stress of main switches is reduced by zero voltage switching. Moreover, the proposed converter doesn't need active PFC switch and auxiliarly circuits, like control and gating board, so it could decrease the size and cost and increase the efficiency.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.16-18
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• 2008

A novel general direct duty ratio pulse width modulation strategy is proposed to modulate matrix converters. By using average concept over one switching period, the modulation algorithm and the required equations are derived to synthesize the desired output voltage and to achieve the controlled input power factor. The proposed method use continuous carrier and the predetermined duty ratio signal for directly generating gating signals an thus is named "direct duty ratio PWM(DDPWM)". The feasibility and validity of the proposed strategy are verified by experimental results.

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.139-141
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• 2000

High voltage direct current(HVDC) transmission system uses the phase controlled rectifier triggered by means of IPC(individual phase control) or EPC(equidistant pulse control). Most HVDC system has adopted EPC method that can solve the harmonic instability problem of IPC method in weak power system. But EPC has inherent indirect synchronizing problem requiring the closed loop control. This paper presents the new gate pulse generating method for 12-pulse HVDC converter, which combines IPC with EPC. Simulation and test results are presented. The basic concept is that it generates the gating pulse for 12-pulse converter by synthesizing the internal phase reference using the frequency and phase information of a sin91e phase voltage. To ensure the reliability of the external phase input, Potential transformer that detects the phase voltage has redundancy. Using fault detecting algorithm the healthy input is always guaranteed. And the frequency compensation function was reinforced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.255-266
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• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.205-213
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• 2002

This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified ｑ-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.662-669
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• 2016

In this work, nonlinear control of a three-phase shunt active power filter (SAPF) has been studied and compared to classical control based on proportional integral regulator. The control strategy is based on the direct current method using sliding mode control (SMC), where the aim is to regulate the average voltage across the dc bus of the inverter. Details are given for the control algorithm; the controller is comprised of a current loop which utilizes a hysteresis controller to generate the gating signals for the switching devices, and a nonlinear controller based on SMC law which is different from classical laws based on error between reference and measured output voltage of the inverter. Sliding surface applied in this work contains the whole of state variables, in order to ensure full control of the system behavior in the presence of disturbances that affect the supply source, the load parameters or the reference value. The designed controller offers advantage that it can gives the improvement of dynamic and static performances in cases of large disturbances. A comparison of the effects of PI control and SMC on the APF response in steady stat, under line variations, load variations, and different component variations is performed.