• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• Journal of Power Electronics
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• v.14 no.1
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• pp.22-29
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• 2014

Current sharing between modules in a converter parallel operation is very important for the reliability of the system. This paper proposes an improved droop method that can effectively improve current sharing accuracy. The proposed method adaptively adjusts the output voltage set-point of each module according to the current set-points. Unlike conventional droop control, modules share a signal line to communicate with each other. Nevertheless, since signals are simple and in digital form, the complexity of the circuitry is much less and noise immunity is much better than those of conventional methods utilizing communication. The operation principle and design procedure of the proposed method are described in detail. Results of the experiment on two boost converters operating in parallel under the specification of a TFT LCD TV panel power supply verify the validity of the proposed scheme.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.531-536
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• 1991

This paper describes a POWER MOSFET inverter suitable for medium frequency induction heating applications. A series scheme is employed, which is operated at zero phase of the resonant load by PLL control. This ensures maximum power transfer, good efficiency, low EMI noise and reliable operation. Circuit configuration and performance are discussed and design criteria are given. Implementation of a prototype rated at 5KW, $100{\sim}300KHz$ is discribed and experimental results are given.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.21-24
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• 2002

This paper presents a fully integrated, wide tuning range differential CMOS voltage-controlled oscillator, tuned by pMOS-varactors. VCO utilizing a novel tuning scheme is reported. Both coarse digital tuning and fine analog tuning are achieved using pMOS-varactors. The VCO were implemented in a 0.18-fm standard CMOS process. The VCO tuned from 1.8㎓ to 2.55㎓ through 2-bit digital and analog input. At 1.8V power supply voltage and a total power dissipation of 8mW, the VCO features a phase noise of -126㏈c/㎐ at 3㎒ frequency offset.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.126-128
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• 2018

Solar array simulator (SAS) is a special DC power supply that regulates the output voltage or current to emulate characteristics of photovoltaic (PV) panels. Especially, the control of SAS is a challenging task due to the nonlinearity in the output curve, which is dependent on irradiance as well as temperature and is determined by panel materials. Conventionally, both current-mode control and voltage-mode control should be alternated by partitioning the operating curve into multiple sections, which is not only for the measurement noise problem with the feedback sensing but also for the control stability issue near the maximum power point. However, the occurrence of transition among different controllers may deteriorate the overall performance. To eliminate the mode transitions, a novel single controller scheme has been introduced in this paper, where the reference operating projection technique enables simple, smooth and numerically stable control. Theoretical consideration on the loop stability issue is discussed and the performance is verified experimentally for the emulation of a PV panel data in view of stability and response speed.

• ETRI Journal
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• v.33 no.6
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• pp.969-972
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• 2011

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-${\mu}m$ CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.4
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• pp.22-29
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• 2002

Usually, much harmonics are included and cause harmonic loss of motor, torque pulsation, electro-magnetic noise and shock etc. by switching function of inverter when drive induction motor variableness inside. It applied partial resonant Buck converter and three phase voltage type SPWM inverter circuit to induction motor driving system in this paper that see to solve such problem. Changed operation condition variously to do input current of circuit that propose sine-wave by unit power factor almost and capacitor supplied bringing back to life voltage by power supply arranging properly assistance diode and electric power switching. Power factor and efficiency improved as that minimize variation of input at power supply voltage polarity reverse by that add voltage reversal function. Also, by using output filter, reduced harmonic of output line to line voltage components, and introduce state space analysis and forecast operation of rectifier. Such all items confirmed validity through simulation and an experiment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.358-365
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• 2008

A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1222-1225
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• 2004

This paper presents multibit Sigma-Delta ADC using noise-shaped dynamic element matching(DEM). 5-bit flash ADC for multibit quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator Using this algorithm, distortion spectra from DAC linearity errors are shaped. Sigma Delta ADC achieves 82dB signal to noise ratio over 615H7z bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is designed to use 0.25um CMOS technology with 2.5V supply voltage and verified by HSPICE simulation.