• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.72-79
• /
• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.9-14
• /
• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of IKEEE
• /
• v.24 no.4
• /
• pp.1129-1135
• /
• 2020

The effects of battery aging limit the rechargeable capacity, State of Health(SoH). It is very important to estimate the SoH in the battery monitoring system(BMS) and many algorithms of measuring the internal resistance of the battery were proposed. A method is used by applying a current source of a specific frequency to the battery and measuring the voltage response. When charging harmonic noise is generated in the voltage response, it results in poor resistance measurement accuracy. In this paper, a robust battery internal resistance measurement algorithm is proposed to eliminate the effect of charging noise by integrating the current source and voltage response signals for a certain period. It showed excellent accuracy and stable measurement results. Applying to the BMS for uninterruptible power supply, the usefulness of the proposed method is verified.

• International Journal of Internet, Broadcasting and Communication
• /
• v.15 no.3
• /
• pp.122-128
• /
• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.113-117
• /
• 2003

The digital systems include the noise in power supply, ground and packaging due to a simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. The requirement for the controlled impedance on a PCB can be both a critical success factor and a design challenge. So, the invented tool simulates the tracks controlled impedance with the test coupon. It can saves the design time and supports the economical PCB design.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.767-770
• /
• 2003

A SiGe HBT MMIC differential VCO has been developed for C-band wireless LAN applications. The VCO produces -6.4 dBm output power at 4.75 GHz. The VCO exhibits a 490 MHz tuning range with control voltage from 0.5 V to 2.5 V. The phase noise of the VCO exhibits -106.5 dBc/Hz at 1 MHz offset from the 4.75 GHz carrier. The total current consumption of the VCO is 10 mA at a supply voltage of 3 V.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.149-153
• /
• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.

• The Journal of the Acoustical Society of Korea
• /
• v.33 no.2
• /
• pp.111-117
• /
• 2014

In this paper, the structure-borne noise reduction on electrical equipment is discussed by the experimental analysis. The water cooling system in electrical equipment is the only noise source, so the mock-up was made to measure noise characteristics. Effects of power supply, stiffness, isolation of noise source and natural frequency determined by resilient mounts are investigated using the mock-up. The console prototype was made referring to noise reduction technique by the mock-up. The structure-borne noise level of a console prototype was measured and some experiments to reduce the noise was undertaken. The $1^{st}$ and $4^{th}$ harmonics of operating frequency of cooling fans causes highest structure-borne noise levels. The control of operating speeds of several DC cooling fan groups was tried. Also types and installation layouts of resilient mounts were investigated. To reduce structure-borne noise, followings can be applied: increase of stiffness, isolation of source, decrease of natural frequency of mount, combination of operating speed of fans, selection of mounts, and so on.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.9
• /
• pp.1027-1034
• /
• 2014

We present the Low Power Broadband Low noise amplifier(LNA) that can be applied a whole bandwidth from 3G to 4G LTE. This multi input LNA was designed to steadily amplify through a multi input method regardless the size of the input signal and operate on a wide range of frequency band from a standard 3G CDMA band 1.2GHz to LTE band 2.5GHz. The designed LNA consumes an average of 6mA on a 1.2V power supply and this was affirmed using computer simulation tests. The amplification which was corresponded to the lowest input signal is at a maximum of 20dB and was able to obtain the minimum value of the gain of -10dB. The Noise figure is less than 3dB at a High-gain mode and is less than 15dB at a Low-gain mode.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.615-623
• /
• 2016

The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a $0.13-{\mu}m$ CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable $V_{DD}$ and by 63% with variable $V_{OUT}$. The power efficiency was improved by 3.5% depending on loading condition.