• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.13-18
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• 2004

전력계통 분야에서는 HVDC 전력변환소, BTB, UPFC 및 SVC의 안정성 향상 및 안정적인 운용을 위한 체계적인 유지보수 및 관리가 필요하다. 특히 전력계통에 접속된 대용량 전력반도체 소자인 사이리스터 밸브는 운전중에 열적, 전기적인 스트레스를 받게 되며, 이로 인해 밸브의 수명이 감소하여 전력계통의 안정적인 운용을 어렵게 만드는 요인이 된다. 따라서 전력계통 운용의 안정성을 확보하기 위해서는 대용량 사이리스터 밸브의 열적, 전기적 스트레스에 따른 수명 변화를 예측하는 열화진단 기법의 개발이 중요하다. 본 고에서는 대용량 사이리스터 소자의 열화진단 기법에 대한 국내외 현황과 현재 연구가 진행중인 열화 진단 기법에 대해 서술하였으며, 1500V급 사이리스터 소자의 가속열화 실험을 통해 소자의 수명을 예측한 결과를 나타내었다.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1785-1787
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• 2003

본 논문에서는 현재 대용량 전력변환 소자인 사이리스터는 해남-제주간의 HVDC변환소에 채용되어 운전중에 있고, BTB 및 SVC등에 채용되고 있으며, 향후 FACTS, 남북 전력계통연계, 동북아 계통연계 등 전력변환용으로 사용될 부품으로 사용범위가 날로 증가하고 있는 2,208개의 사이리스터의 수명 및 신뢰성을 평가하기 위해 고온직류 blocking 가속열화시험조건에 대해서 기술하였다.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.45-48
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• 2007

The proposed method offers an improved DC/DC converter scheme to increase power density. It is based on half-bridge topology with newly introduced pulse-grouping control method, which helps to reduce the transformer size and the volume of semiconductor devices maintaining high efficiency. Test results with 85W(18.5V/4.6A) design shows that the measured efficiency is 93.5% with power density of $36W/in^3$.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.971-976
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• 2011

This paper proposes a test system for a valve and poles building blocks used for large scale inverters such as STATCOM, SSSC, UPFC and VSC HVDC. Power semiconductors in the valve are normally connected in series to withstand switching voltage much larger than the voltage rating of a single power semiconductor. Therefore, there is a need to verify if the dynamic voltage sharing during switching in a valve is satisfactory. In this paper, we propose a test system that provides the necessary test condition: voltage and current in the valve using resonant circuits. A test scheme for a single phase inverter consisting two poles is also proposed. The performance of the inverter pole has to be verified at the factory test, before the system is installed at the site to secure the reliability of the system. The proposed scheme makes it possible to confirm if the pole can withstand voltage and current switching condition and handle loss.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.731-736
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• 2001

Nowadays various simulation tools are widely used for the design and the analysis of power electronic converters. From the engineering point of view it is rather difficult to parameterize power semiconductor device models without the knowledge of basic physical parameters. In recent years some data sheet driven behavioral models or so called 'wizard' tools have been introduced to solve this problem. In this contribution some experiences with some user-friendly power semiconductor models will be discussed. Using special simulation test circuits it is possible to get information on the static and dynamic behavior of the parameterized models before they are applied in more complex schemes. These results can be compared with data sheets or with measurements. The application of these models for power loss analysis of inverter type arc welding power sources will be described.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.203-212
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• 2004

The heat pipe for cooling power semiconductor is required no performance changing during the life cycle up to 20 years. For the long reliable performance of the heat pipe, my reasons that has possibility to generate non condensable gases we not allowed. In this research, the maximum heat transport rate and operation characteristics that are related to various geometric and thermal conditions are carried out. Also the test items, specifications and methods to guarantee the long life cycle of the heat pipe for power semiconductor cooling device are provided and the tests are performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.113-118
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• 2011

According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.