• Title/Summary/Keyword: Power semiconductor devices

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Space Modulation of the Channel Current Density in IGFET by the Polarized Metal Gates (IGFET 채널 전류 밀도의 공간 변조 현상에 관한 연구)

  • 라극환
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.4
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    • pp.31-36
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    • 1984
  • Various efforts have been dedicated to obtain the negative impedances in microwave frequencies with semiconductor devices by many scientists for f: some passed decades, and as a result, many solid state microwave devices have been developed. But they all have much less maximum power ratings with respect to the vaccum tubes. In this paper, a MOSFET is proposed and studied, which have a periodic structure of multigates on the semiconductor via insulator. The hish electric field in the channel induces a voltage distribution on the gates by electrostatic coupling, and the polarization so induced between the gates is able to give a space modulation of the velocity of carriers or the current density in the channel, and as a natural consequence, a microwave amplifier with higher power ratings can be expected.

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AC Servo Motor Control Using Low Voltage High Performance DSP (저전압 고성능 DSP를 이용한 AC 서보모터 제어)

  • 최치영;홍선기
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.1
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    • pp.21-26
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    • 2004
  • Recently with the development of power switching device and DSP which has peripheral devices to control AC servo system, the servo technology has met a new development opportunity. Those things make it possible to reduce the time of developing a AC servo system. Fixed point DSP such as TMS320F240x, and TMS320F28x series have a disadvantage in calculating floating number where TMS320C32 or TMS320C31 are floating point DSP. However they usually become a complex hardware system to implement the AC servo system and it increases the cost. In this study, a DSP based AC servo system with a 3-phase PMSM is proposed. The newly produced DSP TMX320F28l2-version C which has the performance of fast speed, 150MIPS, and a rich peripheral interface such as a 12bit high speed AD converter, QEP(Quadrature Encoder Pulse) circuit, PDPINT(Power Drive Protect Interrupt), SVPWM module and dead time module are used. This paper presents a method to overcome fixed point calculating using scaling all parameters. Also space vector pulse width modulation (SVPWM) using off-set voltage and a digital PI control are implemented to the servo system.

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Electrical and optical characterizations of OSCs based on polymer/fullerene BHJ structures with LiF inter-layer (Polymer/fullerene/LiF inter-layer BHJ 유기태양전지의 광학 및 전기적 특성에 대한 연구)

  • Song, Yoon-Seog;Kim, Seung-Ju;Ryu, S.O.
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.1
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    • pp.27-32
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    • 2011
  • In this study, we have investigated the power conversion efficiency of organic solar cells utilizing conjugated polymer/fullerene bulk-hetero junction(BHJ) device structures. We have fabricated poly(3-hexylthiophene)(P3HT), poly[2methoxy-5-(3',7'-dimethyloctyl-oxy)-1-4-phenylenevinylene] as an electron donor, [6,6]-phenyl $C_{61}$ butyric acid methylester(PCBM-$C_{61}$)as an electron acceptor, and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS) used as a hole injection layer(HIL), after fabricated active layer, between active layer and metal cathode(Al) deposited LiF interlayer(5 nm). The properties of fabricated organic solar cell(OSC) devices have been analyzed as a function of different thickness. The electrical characteristics of the fabricated devices were investigated by means J-V, fill factor(FF) and power conversion efficiency(PCE). We observed the highest PCEs of 0.628%(MDMO-PPV:PCBM-$C_{61}$) and 2.3%(P3HT:PCBM-$C_{61}$) with LiF inter-layer at the highest thick active layer, which is 1.3times better than the device without LiF inter-layer.

Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM

  • Kim, Yong-Sung;Shin, Soo-Ho;Han, Sung-Hee;Yang, Seung-Chul;Sung, Joon-Ho;Lee, Dong-Jun;Lee, Jin-Woo;Chung, Tae-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.2
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    • pp.61-67
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    • 2006
  • We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

Physics-based Algorithm Implementation for Characterization of Gate-dielectric Engineered MOSFETs including Quantization Effects

  • Mangla, Tina;Sehgal, Amit;Saxena, Manoj;Haldar, Subhasis;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.3
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    • pp.159-167
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    • 2005
  • Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

Transient Liquid Phase Diffusion Bonding Technology for Power Semiconductor Packaging (전력반도체 접합용 천이액상확산접합 기술)

  • Lee, Jeong-Hyun;Jung, Do-hyun;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.9-15
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    • 2018
  • This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

Human body model electrostatic discharge tester using metal oxide semiconductor-controlled thyristors

  • Dong Yun Jung;Kun Sik Park;Sang In Kim;Sungkyu Kwon;Doo Hyung Cho;Hyun Gyu Jang;Jongil Won;Jong-Won Lim
    • ETRI Journal
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    • v.45 no.3
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    • pp.543-550
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    • 2023
  • Electrostatic discharge (ESD) testing for human body model tests is an essential part of the reliability evaluation of electronic/electrical devices and components. However, global environmental concerns have called for the need to replace the mercury-wetted relay switches, which have been used in ESD testers. Therefore, herein, we propose an ESD tester using metal oxide semiconductor-controlled thyristor (MCT) devices with a significantly higher rising rate of anode current (di/dt) characteristics. These MCTs, which have a breakdown voltage beyond 3000 V, were developed through an in-house foundry. As a replacement for the existing mercury relays, the proposed ESD tester with the developed MCT satisfies all the requirements stipulated in the JS-001 standard for conditions at or below 2000 V. Moreover, unlike traditional relays, the proposed ESD tester does not generate resonance; therefore, no additional circuitry is required for resonant removal. To the best of our knowledge, the proposed ESD tester is the first study to meet the JS-001 specification by applying a new switch instead of an existing mercury-wetted relay.

Synchronization on the Points of Turn -off Time of Series-Connected Power Semiconductor Devices Using the Miller Effect (전력용 반도체 소자의 직렬연결시 밀러효과를 이용한 소호시점 동기화 알고리즘)

  • 심은용;서범석;이택기;현동석
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.41 no.3
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    • pp.237-243
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    • 1992
  • The large value of the snubber capacitor is needed to protect the devices in high voltage converters using series connected power semiconductors. But that results in more losses and longer commutation time. So, new technique of series connection is required, which can minimize the value of snubber capacitor and also promote the reliability of high voltage converters. We study on the switching characteristics of series connected power semiconductors and then propose a novel switching algorithm for series-connection which is able to implement not only the dynamic voltage balancing in spite of the differerce of switching characteristics, but the minimization of the value of snubber capacitor, through the change of the value of snubber capacitor by Miller effect. Finally, we illustrate the validity of this synchronization by computer simulation and experimental results.

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Diffusion Model of Aluminium for the Formation of a Deep Junction in Silicon (실리콘에서 깊은 접합의 형성을 위한 알루미늄의 확산 모델)

  • Jung, Won-Chae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.4
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    • pp.263-270
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    • 2020
  • In this study, the physical mechanism and diffusion effects in aluminium implanted silicon was investigated. For fabricating power semiconductor devices, an aluminum implantation can be used as an emitter and a long drift region in a power diode, transistor, and thyristor. Thermal treatment with O2 gas exhibited to a remarkably deeper profile than inert gas with N2 in the depth of junction structure. The redistribution of aluminum implanted through via thermal annealing exhibited oxidation-enhanced diffusion in comparison with inert gas atmosphere. To investigate doping distribution for implantation and diffusion experiments, spreading resistance and secondary ion mass spectrometer tools were used for the measurements. For the deep-junction structure of these experiments, aluminum implantation and diffusion exhibited a junction depth around 20 ㎛ for the fabrication of power silicon devices.

Three-Phase PWM Inverter and Rectifier with Two-Switch Auxiliary Resonant DC Link Snubber-Assisted

  • Nagai Shinichiro;Sato Shinji;Matsumoto Takayuki
    • Journal of Power Electronics
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    • v.5 no.3
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    • pp.233-239
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    • 2005
  • In this paper, a new conceptual circuit configuration of a 3-phase voltage source, soft switching AC-DC-AC converter using an IGBT module, which has one ARCPL circuit and one ARDCL circuit, is presented. In actuality, the ARCPL circuit is applied in the 3-phase voltage source rectifier side, and the ARDCL circuit is in the inverter side. And more, each power semiconductor device has a novel clamp snubber circuit, which can save the power semiconductor device from voltage and current across each power device. The proposed soft switching circuits have only two active power semiconductor devices. These ARCPL and ARDCL circuits consist of fewer parts than the conventional soft switching circuit. Furthermore, the proposed 3-phase voltage source soft switching AC-DC-AC power conversion system needs no additional sensor for complete soft switching as compared with the conventional 3-phase voltage source AC-DC-AC power conversion system. In addition to this, these soft switching circuits operate only once in one sampling term. Therefore, the power conversion efficiency of the proposed AC-DC-AC converter system will get higher than a conventional soft switching converter system because of the reduced ARCPL and ARDCL circuit losses. The operation timing and terms for ARDCL and ARCPL circuits are calculated and controlled by the smoothing DC capacitor voltage and the output AC current. Using this control, the loss of the soft switching circuits are reduced owing to reduced resonant inductor current in ARCPL and ARDCL circuits as compared with the conventional controlled soft switching power conversion system. The operating performances of proposed soft switching AC-DC-AC converter treated here are evaluated on the basis of experimental results in a 50kVA setup in this paper. As a result of experiment on the 50kVA system, it was confirmed that the proposed circuit could reduce conduction noise below 10 MHz and improve the conversion efficiency from 88. 5% to 90.5%, when compared with the hard switching circuit.