• Journal of IKEEE
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• v.16 no.2
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• pp.102-108
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• 2012

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.75-76
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• 2007

Several kinds of High Temperature Superconducting(HTS) power cables have already been developed and evaluated for use in the utility power network. HTS power cable is expected to be used as a very powerful energy delivery system supplying electric power for densely populated cities in the near future, because HTS power cable is capable of the high current density delivery with low AC loss and the size effect comparing with the conventional cable whose capacity is same. Before applying the HTS power cable to real utility network system analysis should be carried out by some simulation tools. Hereby the electrical power system analysis is very important for the practical use of HTS power devices. In this paper, authors propose a real-time simulation method which incorporates a real HTS tapes into the simulated 22.9kV utility power network system using Real Time Digital Simulator(RTDS). For the simulation analysis, a test sample of HTS tapes was actually manufactured, and the transient phenomenon of HTS power cable system was analyzed in the simulated utility power network.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.377-382
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• 2010

For business purposes, it is important to identify diffusion power users, a group of users who have big influence on other users in diffusing content. In this paper, we use the independent cascade model for determining diffusion power users, and to do so, we need a method for calculating the assimilation probability between users. This paper proposes the concepts of user delivery power and a way to quantifying the value of this. User delivery power is used to compute the assimilation probability with user content power. We analyze the proposed method by comparing its performance with those of existing methods through experiments using a real blog network data.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.327-332
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• 2016

The routing protocol for low-power and lossy networks (RPL) is an internet protocol based routing protocol developed and standardized by IETF in 2012 to support a wide range of applications for low-power and lossy-networks (LLNs). In LLNs consisting of resource-constrained devices, the energy consumption of battery powered sensing devices during network operations can greatly impact network lifetime. In the case of inefficient route selection, the energy depletion from even a few nodes in the network can damage network integrity and reliability by creating holes in the network. In this paper, a composite energy-aware node metric ($RER_{BDI}$) is proposed for RPL; this metric uses both the residual energy ratio (RER) of the nodes and their battery discharge index. This composite metric helps avoid overburdening power depleted network nodes during packet routing from the source towards the destination oriented directed acyclic graph root node. Additionally, an objective function is defined for RPL, which combines the node metric $RER_{BDI}$ and the expected transmission count (ETX) link quality metric; this helps to improve the overall network packet delivery ratio. The COOJA simulator is used to evaluate the performance of the proposed scheme. The simulations show encouraging results for the proposed scheme in terms of network lifetime, packet delivery ratio and energy consumption, when compared to the most popular schemes for RPL like ETX, hop-count and RER.

• Journal of Power Electronics
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• v.10 no.3
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• pp.320-327
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• 2010

In this paper, multiple offshore wave energy converters with different output characteristics are connected to one power distribution substation. The connection between the power take-off of the different wave energy converters and the electrical power transmission system is presented in order to investigate whether multiple wave energy converters can augment energy yield and improve network integration capabilities. Moreover, the model of an array of wave energy converters is developed with the goal of analyzing the effects of the offshore wave farm on the electrical network to which it is connected. It is also developed to ensure that the electricity generated by the array is sufficiently controllable, and of a quality that can be integrate into the electricity supply network without unduly increasing the cost of connection, production or delivery.

• Journal of electromagnetic engineering and science
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• v.13 no.4
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• pp.233-239
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• 2013

This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

• Smart Media Journal
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• v.13 no.1
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• pp.45-51
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• 2024

Long Range Wide Area Network (LoRaWAN) is a widely adopted Internet of Things (IoT) protocol due to its high range and lower energy consumption. LoRaWAN utilizes Adaptive Data Rate (ADR) for efficient resource (e.g., spreading factor and transmission power) management. The ADR manages these two resource parameters on the network server side and end device side. This paper focuses on analyzing the ADR and Gaussian ADR performance of LoRaWAN. We have performed NS3 simulation under a static scenario by varying the antenna height. The simulation results showed that antenna height has a significant impact on the packet delivery ratio. Higher antenna height (e.g., 50 m) has shown an improved packet success ratio when compared with lower antenna height (e.g., 10 m) in static and mobility scenarios. Based on the results, it is suggested to use the antenna at higher allevation for successful packet delivery.