• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.5
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• pp.39-51
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• 2014

This paper deals with design of a direct-coupled, small-scaled permanent magnet generator (PMG) for wind power application. First, this paper determines rated power and speed of the PMG from measured characteristics of wind turbines. Second, we derive analytical solutions for the open-circuit field in order to determine optimum magnet thickness and pole pitch/arc ratio. Third, on the basis of open circuit field solutions, stator magnetic circuit including slot opening, teeth width and yoke thickness is designed. And then, a diameter of stator coil which agree with a required current density is calculated, and its turns are determined from the area of slot considering winding packing factor. Finally, finite element (FE) method is employed in analyzing the details of the designed PMG and, test results such as back-emf measurements are given to confirm the design.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.729-733
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• 2003

Hybrid RMU is a kind of power circuit breaker and protects electric devices from over-current. In this paper we built a dynamic model of RMU driving mechanism using ADAMS and performed a optimal design of several design parameters. Finally we developed a prototype of RMU driving mechanism through results of analysis and confirmed it to satisfy design requisitions.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.371-373
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• 2001

Main functions of Generator Circuit Breaker(GCB) is cut the generator off from the main transformers and the aux. transformers when plant trip or startup. In this paper, the design requirements For GCB of nuclear power plant is examined. NRC presented the area of review, acceptance criteria and review procedures of GCB in the SRP(Standard Review Plan). In Korea, APR1400 adapted the GCB in main power system.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.514-517
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• 1998

This paper proposed a symmetric feedback current enhancement circuit with 1.5V power supply to design a 3$^{rd}$ order butterworth low pass filter. The proposed filter designed on 0.8.mu.m CMOS n-well double poly/double metal process simulated in HSPICE composed of the 3dB frequency enhancement circuit and the unity-gain frequency enhancement circuit. The simulation result on the design filter shows the badnwith of 25MHz, phase of 92.6 .deg. and power consumption of 0.3mW..

• Journal of Power Electronics
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• v.16 no.4
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• pp.1256-1267
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• 2016

Distributed stray inductance exerts a significant influence on the turn-off voltages of power switching devices. Therefore, the design of low stray inductance bus bars has become an important part of the design of high-power converters. In this study, we first analyze the operational principle and switching transient of a T-type converter. Then, we obtain the commutation circuit, categorize the stray inductance of the circuit, and study the influence of the different types of stray inductance on the turn-off voltages of switching devices. According to the current distribution of the commutation circuit, as well as the conditions for realizing laminated bus bars, we laminate the bus bar of the converter by integrating the practical structure of a capacitor bank and a power module. As a result, the stray inductance of the bus bar is reduced, and the stray inductance in the commutation circuit of the converter is reduced to more than half. Finally, a 10 kVA experimental prototype of a T-type converter is built to verify the effectiveness of the designed laminated bus bar in restraining the turn-off voltage spike of the switching devices in the converter.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.137-142
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• 2023

When designing a SMPS(Switched Mode Power Supply) circuit, a part that is easily overlooked without special consideration is a snubber circuit. However, the performance degradation of the SMPS due to the snubber circuit and the effect on the entire SET cannot be ignored. In addition, a snubber circuit is added to both ends of the switch to protect the device from peak voltage and current during switching and to reduce loss during on/off switching. Therefore, in this paper, for a sufficient understanding of snubber circuits, theoretical analysis and experimental formulas that can be applied by designers during actual circuit design are arranged to promote optimization of snubber circuits.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.20-29
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• 1998

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.