• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.38-40
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• 2002

A study on the test method and the test facilities of synthetic capacitive current tests have been very slight and the direct test method with the short-circuit generator and power transformer only used up to now. However, according to the development of analysis technique of power system and design and manufacture technique we are realized that direct testing method is not satisfactory to evaluate the performance of circuit-breaker because it is difficult to simulate precisely the conditions of power system. Therefore, in order to solve these problem this paper deals with the tests methods and the design technique of the tests facilities of the synthetic capacitive current based on the same theory with the synthetic short-circuit tests.

• Journal of Power System Engineering
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• v.1 no.1
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• pp.144-153
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• 1997

The magnetic levitation system is utilized in the magnetic bearing of high-speed rotor because of little friction, no lubrication, no noise and so on. The magnetic levitation system need the feedback controller for the stabilization of system, and gap sensors are generally used to measure the gap. The use of gap sensors brings out the increase of the number of troublesome, and the decrease of the control performance because of the dislocation between the measurement point and the control point. This paper presents the design of the gap estimation circuit for the sensorless method proposed by authors in the magnetic levitation system. We made the gap estimation circuit which was composed of both the superposition circuit and the measuring circuit. And we investigated the validity of the usefulness of the proposed sensorless method in the magnetic levitation system through results of actual experiment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.837-843
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• 2008

This paper proposes a power divider based on meta-material structure with dual-band operation. The meta-material structures of left-hand characteristic are constituted of series capacitors and shunt inductors, but they have parasitic series inductance and shunt capacitance effects. There is represented the composite right/ left-handed transmission line (CRLH-TL) model. When the power divider is implemented by using the CRLH-TL, the power divider can operate dual band. To verify the power divider with dual band, we are implemented to operate dual-band that is 0.88 GHz and 1.67 GHz. The characteristics of divider have the return loss less than each 21.0 dB and 15.8 dB and the insertion loss better than 3.83 dB and 3.64 dB at each frequency. Also, the output phase difference is $3{\sim}6^{\circ}$.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.41-60
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• 1995

The IGBT(Insulated Gate Bipolar Transistor) is a power semiconductor device that has gained acceptance among circuit design engineers for motor drive and power converter applications. IGBT devices(International Rectifier, Proposed proposed model etc) have the best features of both power MOSFETs and power bipolar transistors, i.e., efficient voltage gate drive requirememts and high current density capability. When designing circuit and systems that utilize IGBTs or other power semiconductor devices, circuit simulations are needed to examine how the devices affect the behavior of the circuit. The interaction of the IGBT with the load circuit can be described using the device model and the state equation of the load circuit. The voltage rise rate at turn-off for inductive loads varies significantly for IGBTs with different base life times, and this rate of rise is important in determing the voltage overshoot for a given series resistor-inductor load circuit. Excessive voltage overshoot is potentially destructive, so a snubber protection circuit may be required. The protection circuit requirements are unique for the IGBT and can be examined using the model. The IGBT model in this paper is verified by comparing the results of the model with experimented results for various circuit operating conditions. The model performs well and describes experimented results accurately for the range of static and dynamic condition in which the device is intended to be operated.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.7
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• pp.1199-1205
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• 2010

The recent power system is required to a large size of facilities and high power technology according to increasing power demand. However, it could lead to spoiling the beauty of city and environment problem. The miniaturized facilities with large capacity such as GIS have been required in recent power system. The GIS(Gas Insulated Substation) using the SF6 insulation gas enables to miniaturize facilities with large capacity with high insulation performance. However, the substation installed GIS has required to new design model which is different from the conventional substation. The TRV(Transient Recovery Voltage) analysis on simple circuit may applied by differential equation. However, in case of relatively complicated system, EMTP(Electro Magnetic Transients Program) mainly has been used to design and simulate for transient analysis. This paper mainly design the 22.9 kV GIS system and analyze the transient recovery voltage of main circuit breaker using EMTP/RV. It also enables to easily design the other substation installed GIS with same maker and voltage level because the proposed GIS model consists of separated modules such as busbar, circuit breaker, bushing, CT, PT etc. Eventually, it contributes to comfortably compare the interrupting performance of circuit breaker and system TRV corresponding to the substation system configuration.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.5
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• pp.389-394
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• 2015

This paper proposes a series-connected power conversion system that integrates a photovoltaic power conditioner and a charge-balancing circuit. In conventional methods, a photovoltaic power conditioner and a cell-balancing circuit are needed for photovoltaic systems with energy storage devices, which results in a complex configuration and high cost. To overcome these problems, a series-connected DC-DC power conditioning system that integrates a photovoltaic power conditioner with a charge-balancing circuit is proposed. During the generation, the system operates as power conditioner only, whereas it operates as a cell balancing circuit during the rest time. For the analysis, the operating principle of the circuit and the controller design are done by PSIM simulation. For verification, a hardware prototype with 48-W photovoltaic modules has been implemented. Results verified that the modularized photovoltaic power conversion system with a series-connected storage successfully works with the proposed method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.