• Title/Summary/Keyword: Power circuit design

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7×7 MIMO System Using Extended 13-Element ESPAR Antenna (확장 13-Element EPSAR 안테나를 사용한 7×7 MIMO 시스템)

  • Bok, Junyeong;Lee, Seung Hwan;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39A no.2
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    • pp.69-76
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    • 2014
  • Multiple-input and multiple-output (MIMO) technique is used in many communication fields in order to increase the channel capacity. However, this MIMO system has difficulty of miniaturization of antenna size due to the multiple RF chains Also, multiple RF chain raises some problems which increase power consumption at RF circuit and degrade the system performance due to the interference between RF chains. Because of these reasons, beamspace MIMO (BS-MIMO) technique with only single RF chain was proposed for MIMO transmission. This BS-MIMO system basically uses electronically steerable parasitic array radiator (ESPAR) antenna. Existing ESPAR antenna has a 5-element structure. So, it is possible to do only $3{\times}3$ MIMO transmission. Therefore, in order to extend BS-MIMO dimension, extension of ESPAR antenna structure is essential. In this paper, we show that BS-MIMO dimension can be increased according to the extension of structure of the ESPAR antenna, as in the conventional MIMO techniques. For example, we show that it is possible to design the $7{\times}7$ BS-MIMO transmissions with the 13-element ESPAR antenna. Also, when the number of parasitic elements of ESPAR antenna increases by two elements, MIMO dimension is expanded by 1.

Design of the 1.9-GHz CMOS Ring Voltage Controlled Oscillator using VCO-gain-controlled delay cell (이득 제어 지연 단을 이용한 1.9-GHz 저 위상잡음 CMOS 링 전압 제어 발진기의 설계)

  • Han, Yun-Tack;Kim, Won;Yoon, Kwang-Sub
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.72-78
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    • 2009
  • This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

Design of a Multi-Band Low Noise Amplifier for 3GPP LTE Applications in 90nm CMOS (3GPP LTE를 위한 다중대역 90nm CMOS 저잡음 증폭기의 설계)

  • Lee, Seong-Ku;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.100-105
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    • 2010
  • A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

A Flipflop with Improved Noise Immunity (노이즈 면역을 향상시킨 플립플롭)

  • Kim, Ah-Reum;Kim, Sun-Kwon;Lee, Hyun-Joong;Kim, Su-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.8
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    • pp.10-17
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    • 2011
  • As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

Design and Analysis of a NMOS Gate Cross-connected Current-mirror Type Bridge Rectifier for UHF RFID Applications (UHF RFID 응용을 위한 NMOS 게이트 교차연결 전류미러형 브리지 정류기의 설계 및 해석)

  • Park, Kwang-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.10-15
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    • 2008
  • In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

The Design of Low Noise Amplifier for Overall IMT-2000 Band Repeater (IMT-2000 중계기용 전대역 저잡음 증폭기 설계)

  • 유영길
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.4
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    • pp.409-412
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    • 2002
  • The LNA(Low Noise Amplifier) is designed for use in low cost commercial application covered fully IMT-2000 band(1920~2170MHz, BW=250MHz). It is optimized source inductance for source lead and designed to equivalent etched line. The LNA uses a high pass impedance matching network for noise match and simple structure. The bias circuit designs have been made self-biased with a negative voltage applied to gate. The power supply voltage is 8V, total current is 180mA. The LNA is biased at a Vgs of -0.4, Vds of 4V for first stage and Vds of 5V for second stage. The LNA is designed competitively for commercial product specification. The measured gain and noise figure of the completed amplifier was 20dB and 1dB, respectively. Also, input VSWR, P1dB and gain flatness was measured of 1.14 ~ l.3dB, 22.4dBm and $\pm$0.45dB, respectively. The designed LNA can be used for commercial product.

A Study on the Design of Dual-Band Mixer for WLAN 802.11a/b/g Applications (802.11a/b/g WLAN용 이중대역 혼합기 설계에 관한 연구)

  • Park Wook-Ki;Go Min-Ho;Kang Suk-Youb;Park Hyo-Dal
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.11 s.102
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    • pp.1106-1113
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    • 2005
  • This paper presents a dual-band mixer for multi-standards of IEEE 802.1la/b/g using a single local oscillator, so as to improve the defects of legacy systems. Those systems have duplicate local oscillators and mixers to handle dual band signals, increasing complexity of system and power loss. The proposed circuit shows 11.6 dB, 16.8 dB of conversion loss and 8.77 dBm, 12.5 dBm of IIP3(Input 3rd Intercept Point) for respective bands when the two RF inputs of 2.452 and 5.260 GHz are down-converted to the identical 356 MHz If frequency. The RF-LO isolations are measured 36 dB, 41 dB at each frequencies and over 50 dB of LO-IF isolations are achieved at all cases.

Design and Analysis of 45°-Inclined Linearly Polarized Substrate Integrated Waveguide(SIW) Slot Sub-Array Antenna for 35 GHz (45도 선형 편파 발생용 SIW 슬롯 Sub-Array 안테나 설계 및 해석)

  • Kim, Dong-Yeon;Nam, Sangwook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.4
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    • pp.357-365
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    • 2013
  • The 4 by 4 series slot sub-array antenna is proposed using substrate integrated waveguide(SIW) technology for 35 GHz of Ka band application. The proposed antenna is realized with multi-layered structure for compact size and easy integration features. 4 by 4 radiating slots are arrayed on top PCB with equal spacing and the feeding SIWs are arranged on middle and bottom PCBs for uniform power distribution. The multi-layered antenna is realized using RT/Duroid 5880 that has dielectric constant of 2.2 and the total antenna size is $750.76mm^2$. The individual parts such as radiators and feeding networks are simulated using full-wave simulator CST MWS. Furthermore, the total sub-array antenna also fabricated and measured the electrical performances such as impedance bandwidth under the criteria of -10 dB(490 MHz), maximum gain(18.02 dBi), sidelobe level(SLL)(-11.0 dB), and cross polarization discrimination (XPD)(-20.16 dB).

Design and Implementation of VCO for Doppler Radar System (도플러 레이더 시스템용 VCO 설계 및 제작)

  • Kim Yong-Hwan;Kim Hyun-Jin;Min Jun-Ki;Yoo Hyung-Soo;Lee Hyung-Kyu;Hong Ui-Seok
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.4 no.2 s.7
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    • pp.81-87
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    • 2005
  • In this paper, a VCDRO(Voltage Control Dielectirc Resonator Oscillator) for signal source of doppler radar system is designed and fabricated. The proposed VCDRO is made with new tuning mechanism using CPW line. The coplanar waveguide of $\lambda_{g}$/2 in length with varactor diode is placed on the metallization side under the dielectric resonator and coupled to it. Tuning varactor diode is mounted at one end of the CPW. The proposed circuit tuned by a CPW allows one more varactor diode to be mounted on the optimized CPW, where a greater sensitivity of frequency tuning is needed. With varying the biasing voltage for the varactor diode from 0 V to 15 V, output frequency tuning of 12 MHz is obtained. The PLDRO exhibits output power of 16.5 dBm with phase noise in the phase locked state characteristic of -115 dBc/Hz at 100 Hz, -105 dBc/Hz at the 10 kHz, and -102 dBc/Hz at 1 Hz offset from 10.525 GHz , respectively.

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Economic Analysis of Optical Communication Control System in High Voltage Magnetizer (고전압 착자기에서의 누전 사고 방지를 위한 광통신 제어시스템의 도입 방안과 경제성 분석)

  • Bae, Young Woo;Kim, Wooju;Hong, June Seok
    • Journal of Information Technology Applications and Management
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    • v.26 no.6
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    • pp.103-117
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    • 2019
  • Demand for high power motors is rapidly increasing as the 4th industry and convergence technology has recently emerged. In order to produce high-strength permanent magnets, the magnets used for magnetization have been increased from DC 300V in the 1970s to DC 2.5kV in the 2010s, Up to DC 10kV in the 2030s, It is expected that higher voltage will be used to magnetize. However, in the case of a magnetizer using an existing electric signal control device, it is necessary to use a control device with a high-voltage insulation function in case a high voltage used for magnetization is leaked to the control device. If a short circuit accident occurs, the controller must be shut down and serious problems such as excessive repair costs arise. In this study, a control system adopting optical communication method instead of electric signal control method is proposed to prevent leakage currents in high-voltage magnetizer. We design a transmitter(Tx) and a receiver(Rx) device for the optical communication control device and implemented a prototype connecting the optical cable. In order to demonstrate the utility of high-voltage magnetizer using the optical communication control device, we analyzed the initial cost and the yearly cost for the years to analyze the net present value. As a result, In the case of the low-voltage magnetizer, the electric signal control method cost less, As the operating voltage of the magnetizer becomes higher. It is confirmed that it takes less cost when the optical communication control device is used.