• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.135-144
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• 2008

A bootstrap circuit is widely used for the floating gate power supply of Intelligent power module (IPM). A bootstrap circuit is simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. And the value of the bootstrap capacitor should be increased as the switching frequency decreases. A charge pump circuit can be used to overcome the problems. This paper deals with an analysis and design of a charge pump circuit for the floating gate power supply of an IPM. The simulation and experiment are carried out for an induction motor drive system. The results well verifies the validity of the proposed circuit and design method.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.113-118
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• 2009

This paper is about design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the power line communication (PLC) system. The Tchebycheff gain function algorithm is represented to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.258-262
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• 2010

This paper represents design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the broadband power line communication(BPLC) systems. The Butterworth gain function equalizer is used to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC Coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.638-641
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• 2001

Connectorless power transmission and supply are the power transfer device revealed by resonant inverter or transformer using inductant device. Recently, on power supply have been going on frequently, so several power supply circuit forms are announced. But Compared with the circuit of previous paper, instead of the circuit composed of a simple sylinder Ferrit, I was manufacture in a sylinder that It was a double overlab to a sylinder and I was followed a double flux in inner flux path. Above all, for practicalization, supply circuit operation character analysis and development of controller should be preceded. According to this paper, power transmission and supply analyze characters and design control circuit like the analysis of general resonant inverter for power transmission. They compose the circuit to get sinusoid wave output voltage using pulse width modulation control mode. For Supply, output wave form through power track and power pick-up of magnetic inductance includes ripper component. So I intend to design the controller including filter and regulator, compare analyze theoretical result with real measurement value and then show you their practicality

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.2
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• pp.357-362
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• 2020

The TMFT, a sub-system of TINC, provides voice calls, data transmission and reception, and multimedia services to individual users. At the time of development in 2011, the power circuit of the TMFT was designed to electrical power supply to each device via a charger IC. However, the newly improved power supply circuit allows power to be supplied to each device through the PMIC without configuring the charger IC separately. In this paper, the power circuit design structure of TMFT applied in the development stage and the improved power circuit design structure were compared. And we verified through experiments whether the improved power circuit can be applied to TMFT. The experimental method was verified by directly comparing the current consumption test, charge time comparison test, and rising temperature test during charging each of before and after improvement terminals.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.