• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.354-355
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• 2013

최근 디스플레이 분야에서 amorphous InGaZnO (a-IGZO) thin film transistors (TFTs)는 a-Si:H에 비해 비정질 상태에서도 비교적 높은 이동도를 가지고 다결정 Si 반도체에 비해 저온공정이 가능하고 대면적화가 용이한 장점 때문에 주목받고 있다. 또한 넓은 밴드갭을 가지기 때문에 가시광선 영역에서 투명하여 투명소자에도 응용이 가능하다. 본 연구에서는 RF magnetron sputtering법을 이용하여 RF power의 변화에 따라 IGZO 박막의 positive bias stress (PBS)에 대한 안정성을 조사하였다. 소결된 타겟으로는 In:Ga:ZnO를 각각 2:2:1 mol%의 조성비로 소결하여 이용하였고, 공정 조건은 초기 압력 Torr, 증착 압력 Torr, Ar：O2=18：12 sccm로 고정하였다. 공정 변수로는 130 W, 150 W, 170 W, 200 W로 변화를 주어 실험을 진행하였다. PBS 측정은 gate bias를 10 V로 고정하여 stress 시간을 각각 0, 30, 100, 300, 1,000, 3,000, 7,000초를 적용하였다. 측정 결과 RF power가 증가할수록 문턱전압의 변화량이 증가하는 것을 보였다. 130 W의 경우 4.47 V의 변화량을 보였지만 200 W의 경우는 10.01 V로 증가되어 나타났다. 따라서 RF power을 낮추어 만들어진 소자의 경우 RF power를 높여 만들어진 소자에 비해 PBS에 대한 안정성이 더 높은 결과를 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.65-73
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• 2002

Two CMOS composite transistors with an improved operating region by reducing the threshold voltage are proposed in this paper. And also, as an application of the proposed composite transistors, the transconductor is designed. The proposed composite transistor I and II employ a P-type folded composite transistor and a composite diode in order to decrease the threshold voltage, respectively. The limitation of the operating region of these transistors by current source is described. All circuits are simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.106-111
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• 2016

Thermal noise generated in the electrolyte is modeled for the electrolyte-oxide-semiconductor field-effect transistors. Two noise sources contribute to output noise currents. One is the thermal noise generated in the bulk electrolyte region, and the other is the thermal noise from the double-layer region at the electrolyte-oxide interface. By employing two slightly-different equivalent circuits for two noise current sources, the power spectral density of output noise current is calculated. From the modeling and simulated results, the bulk electrolyte thermal noise dominates the double-layer thermal noise. Electrolyte thermal noise are computed for three different concentrations of NaCl electrolyte. The derived formulas give a good agreement with the published experimental data.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.304.1-304.1
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• 2014

Flat-panel displays have been growing as an essential everyday product in the current information/communication ages in the unprecedented speed. The forward-coming applications require light-weightness, higher speed, higher resolution, and lower power consumption, along with the relevant cost. Such specifications demand for a new concept-based materials and applications, unlike Si-based technologies, such as amorphous Si and polycrystalline Si thin film transistors. Since the introduction of the first concept on the oxide-based thin film transistors by Hosono et al., amorphous oxide thin film transistors have been gaining academic/industrial interest, owing to the facile synthesis and reproducible processing despite of a couple of shortcomings. The current work places its main emphasis on the binary oxides composed of ZnO and SnO2. RF sputtering was applied to the fabrication of amorphous oxide thin film devices, in the form of bottom-gated structures involving highly-doped Si wafers as gate materials and thermal oxide (SiO2) as gate dielectrics. The physical/chemical features were characterized using atomic force microscopy for surface morphology, spectroscopic ellipsometry for optical parameters, X-ray diffraction for crystallinity, and X-ray photoelectron spectroscopy for identification of chemical states. The combined characterizations on Zn-Sn-O thin films are discussed in comparison with the device performance based on thin film transistors involving Zn-Sn-O thin films as channel materials, with the aim to optimizing high-performance thin film transistors.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.334-334
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• 2012

Transparent oxide semiconductors have recently attracted much attention as channel layer materials due to advantageous electrical and optical characteristics such as high mobility, high stability, and good transparency. In addition, transparent oxide semiconductor can be fabricated at low temperature with a low production cost and it permits highly uniform devices such as large area displays. A variety of thin film transistors (TFTs) have been studied including ZnO, InZnO, and InGaZnO as the channel layer. Recently, there are many studies for substitution of Ga in InGaZnO TFTs due to their problem, such as stability of devices. In this work, new quaternary compound materials, tantalum-indium-tin oxide (TaInSnO) thin films were fabricated by using co-sputtering and used for the active channel layer in thin film transistors (TFTs). We deposited TaInSnO films in a mixed gas (O2+Ar) atmosphere by co-sputtering from Ta and ITO targets, respectively. The electric characteristics of TaInSnO TFTs and thin films were investigated according to the RF power applied to the $Ta_2O_5$ target. The addition of Ta elements could suppress the formation of oxygen vacancies because of the stronger oxidation tendency of Ta relative to that of In or Sn. Therefore the free carrier density decreased with increasing RF power of $Ta_2O_5$ in TaInSnO thin film. The optimized characteristics of TaInSnO TFT showed an on/off current ratio of $1.4{\times}108$, a threshold voltage of 2.91 V, a field-effect mobility of 2.37 cm2/Vs, and a subthreshold swing of 0.48 V/dec.

• Proceedings of the KIEE Conference
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• 1984.07a
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• pp.207-208
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• 1984

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.40-46
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• 2001

In this paper, a novel low power full adder circuit comprising only 10 transistors is proposed. The circuit is based on the six -transistor CMOS XOR circuit, which generates both XOR and XNOR signals and pass transistors. This adder circuit provides a good low power characteristics due to the smaller number of transistors and the elimination of short circuit current paths. Layouts have been carried out using a 0.65 ${\mu}m$ ASIC design rule for evaluation purposes. The physical design has been evaluated using HSPICE at 25MHz to 50MHz. The proposed circuit has been used to build 2bit and 8bit ripple carry adders, which are used for evaluation of power consumption, time delay and rise and fall time. The proposed circuit shows substantially improved power consumption characteristics, about 70% lower than transmission gate full adder (TFA), and 60% lower than a design using 14 transistors (TR14). Delay and signal rise and fall time are also far shorter than other conventional designs such as TFA and TR14.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.462-465
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• 1991

In this paper, a newly developed uninterruptible power supply adopted insulated gate bipolar transistors (IGBT'S) is introduced. The focus is on harmonic reduction, high efficiency and so on. The overview, hardware and software of the newly developed ups system are also discussed. Finally, the merit of the newly developed ups compared with conventional ups is described.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.505-508
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• 2006

Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.