• Title/Summary/Keyword: Power Transistors

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Technological Trends of C-/X-/Ku-band GaN Monolithic Microwave Integrated Circuit for Next-Generation Radar Applications (차세대 레이더용 C-/X-/Ku-대역 GaN 집적회로 기술 동향)

  • Ahn, H.K.;Lee, S.H.;Kim, S.I.;Noh, Y.S.;Chang, S.J.;Jung, H.U.;Lim, J.W.
    • Electronics and Telecommunications Trends
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    • v.37 no.5
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    • pp.11-21
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    • 2022
  • GaN (Gallium-Nitride) is a promising candidate material in various radio frequency applications due to its inherent properties including wide bandgap, high carrier concentration, and high electron mobility/saturation velocity. Notably, AlGaN/GaN heterostructure field effect transistor exhibits high operating voltage and high power-density/power at high frequency. In next-generation radar systems, GaN power transistors and monolithic microwave integrated circuits (MMICs) are significant components of transmitting and receiving modules. In this paper, we introduce technological trends for C-/X-/Ku-band GaN MMICs including power amplifiers, low noise amplifiers and switch MMICs, focusing on the status of GaN MMIC fabrication technology and GaN foundry service. Additionally, we review the research for the localization of C-/X-/Ku-band GaN MMICs using in-house GaN transistor and MMIC fabrication technology. We also discuss the results of C-/X-/Ku-band GaN MMICs developed at Defense Materials and Components Convergence Research Department in ETRI.

A 2.4-GHz CMOS Power Amplifier with a Bypass Structure Using Cascode Driver Stage to Improve Efficiency (효율 개선을 위해 캐스코드 구동 증폭단을 활용한 바이패스 구조의 2.4-GHz CMOS 전력 증폭기)

  • Jang, Joseph;Yoo, Jinho;Lee, Milim;Park, Changkun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.8
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    • pp.966-974
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    • 2019
  • In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

A Study on the Design and Electrical Characteristics Enhancement of the Floating Island IGBT with Low On-Resistance

  • Jung, Eun-Sik;Cho, Yu-Seup;Kang, Ey-Goo;Kim, Yong-Tae;Sung, Man-Young
    • Journal of Electrical Engineering and Technology
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    • v.7 no.4
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    • pp.601-605
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    • 2012
  • Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.

Characteristics of P-channel SOI LDMOS Transistor with Tapered Field Oxides

  • Kim, Jong-Dae;Kim, Sang-Gi;Roh, Tae-Moon;Park, Hoon-Soo;Koo, Jin-Gun;Kim, Dae-Yong
    • ETRI Journal
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    • v.21 no.3
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    • pp.22-28
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    • 1999
  • A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURE (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at $V_{gs}$=-0.5V, the specific on-resistance of the LDMOS with the tapered field oxide is about $31.5{\Omega}{\cdot}cm^2$, while that of the LDMOS with the conventional field oxide is about $57m{\Omega}{\cdot}cm^2$.

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Turn-on Loss Reduction for High Voltage Power Stack Using Active Gate Driving Method

  • Kim, Jin-Hong;Park, Joon Sung;Gu, Bon-Gwan;Won, Chung-Yuen
    • Journal of Electrical Engineering and Technology
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    • v.12 no.2
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    • pp.632-642
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    • 2017
  • This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.

CMOS on-chip voltage and current reference circuits for low-voltage applications (저전압용 CMOS 온-칩 기준 전압 및 전류 회로)

  • 김민정;이승훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.4
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    • pp.1-15
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    • 1997
  • This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

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Micro IGBT Device Modeling and Circuit Simulation (미시적인 IGBT 소자 모델링과 회로동작 시뮬레이션)

  • Seo, Young-Soo;Baek, Dong-Hyun;Lim, Young-Bae;Kim, Young-Chun;Cho, Moon-Taek;Seo, Soo-Ho
    • Proceedings of the KIEE Conference
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    • 1994.07a
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    • pp.562-564
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    • 1994
  • IGBT devices have the best features of both power MOSFETs and power bipolar transistors, i. e., efficient voltage gate drive requirements and high current density capability. The interaction of the IGBT with the load circuit can be described using the device model and the state equation of the load circuit. The protection circuit requirements are unique for the IGBT and can be examined using the model.

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Design of a CMOS DC-to-DC Converter for Portable Devices (휴대용 기기를 위한 CMOS DC-DC 변환기 설계)

  • O, N.G.;Lee, J.K.;Cho, I.H.;Jang, S.H.;Cha, C.H.;Yu, C.G.
    • Proceedings of the KIEE Conference
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    • 2008.10b
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    • pp.520-521
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    • 2008
  • This paper describes a low voltage, low-power CMOS buck DC/DC converter, which has a simple common-gate current sensing circuit. It consumes low power because it includes less transistors than other converters which use operational amplifiers for current sensing. The designed DC-DC converter is fabricated in a 0.18um CMOS technology. A maximum efficiency of 88% has been obtained with the proposed circuit. It has $2V{\sim}3.7V$ input voltage range, $1V{\sim}2.5V$ output voltage range and maximum output current of 1000mA.

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A Study on the Design of the Class E Resonant Rectifier with a Series Capacitor (직력 캐패시터를 가진 E급 공진형 정류기 설계에 관한 연구)

  • 김남호
    • Journal of Advanced Marine Engineering and Technology
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    • v.22 no.3
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    • pp.343-352
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    • 1998
  • Higher frequency of energy transfer or at least energy conversion has to be used in order to reduce the size of inductors and capacitors required in the power supplies. Conventional PWM switching-mode power supplies have a limitation of operating frequency due to switching losses in the switching transistors and rectifier diodes. Means of reducing switching losses have been developed for high-frequency resonant amplifiers or more exactly dc/ac inverters. Because of smooth current and voltage waveforms resonant convertesrs havelower device switching losses and stresses lower electromagnetic interference(EMI) and lower noise than PWM converters. Therefore in this paper design equations of Classs E resonant low dv/dt rectifier with a series resonant capacitor drived using Fourier series techniques. The theory is compared with simulation results obtained for the rectifier operating at 10[MHz] ac input and 5[V] coutput.

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ZC-ZVS PWM DC-DC Converter using One Auxiliary Switch (단일 보조 스위치를 이용한 ZC-ZVS PWM DC-DC 컨버터)

  • Park, J.M.;Park, Y.J.;Suh, K.Y.;Mun, S.P.;Kim, Y.M.
    • Proceedings of the KIEE Conference
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    • 2003.07e
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    • pp.158-161
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    • 2003
  • A new soft switching technique that improves performance of the high power factor boost rectifier by reducing switching losses is introduced. The losses are reduced by air active snubber which consists of an inductor, a capacitor a rectifier, and an auxiliary switch. Since the boost switch turns off with zero current, this technique is well suited for implementations with insulated gate bipolar transistors. The reverse recovery related losses of the rectifier are also reduced by the snubber inductor which is connected in series with the boost switch and the boost rectifier. In addition, the auxiliary switch operates with zero voltage switching. A complete design procedure and extensive performance evaluation of the proposed active snubber using a 1.2[kW] high power factor boost rectifier operating from a $90[V_{rms}]$ input are also presented.

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