• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.255-256
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• 2016

This paper is presents a initial starting of SST with high voltage level source. Rush current flowing as difference between capacitor level and grid level can crush the whole system. Thus, industries have used initial constituted by resistance and relay. However the initial circuit used in industries can't apply high voltage application due to isolation and economic feasible problems. Therefore many countries study method can charge capacitor with another voltage sources. Also this paper introduce method charging primary side capacitor efficiently.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.562-564
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• 2008

This paper deals with the three phase high voltage power-grid connection topology using multi-level inverter. Due to the multi-level inverter, these are improved effect of fluctuating voltage, problem of EMC and switching loss using suitable switching patterns of device, above all thing, it is easy to realize the system because of using lower voltage rating switch. This topology can be applicable to power-grid connection of wind system, there is a good point about economical efficiency. The simulation results are presented to verify the validity of the proposed topology.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.869-873
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• 1987

In this study, we have examined the multi-level QPRS system in point of error rate, which requires narrow bandwidth and has Little ISI. The generalized error rate equations of multi-level QPRS signal have been derived in the presence of Gaussian noise and co-channel CW interference. And the error rate performance of 9, 49, 225 QPRS system is investigated as parameters of carrier power-to-noise power, carrier power-to -interference power. Also, we have investigated the effect of carrier offset.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2018.05a
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• pp.37-38
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• 2018

BIM(Building Information Modeling) in the architecture, VDC(Virtual Design and Construction) defined CIFE(Center for Integrated Facility Engineering) of Stanford university in USA, and Data-driven design definition issued by TECDOC-1284 of IAEA are doing data-level design generated by 3D CAD technology, integrating and managing related information based on the 3D model, and Using 3D models effectively during nuclear power plant life cycle. 3D model of domestic nuclear power industry is using interference review between design fields, 4D system linked 3D construction model and schedule activity, but the 3D model generated in the design phase is effectively not utilized during the construction, operation, decommissioning. therefore, This study is aimed to suggest 3D model LOD(Level of Detail) advancement method through the analysis of existing literature, 2D drawings, and 3D models throughout nuclear power plant lifecycle.

• Journal of Power Electronics
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• v.16 no.3
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• pp.925-935
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• 2016

This paper proposes a new interleaved double-input three-level Boost (DITLB) converter, which is composed of two boost converters indirectly in series. Thus, a high voltage gain, together with a low component stress and a small input current ripple due to the interleaved control scheme, is achieved. The operating principle of the DITLB converter under the individual supplying power (ISP) and simultaneous supplying power (SSP) mode is analyzed. In addition, closed-loop control strategies composed of a voltage-current loop and a voltage-balance loop, have been researched to make the converter operate steadily and to alleviate the neutral-point imbalance issue. Experimental results verify correctness and feasibility of the proposed topology and control strategies.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.1
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• pp.43-47
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• 2016

This system is a diagnosis system that checks whether it causes a partial discharge of a power cable or not. It is to classify normal from abnormal-normal, PD (Partial Discharge) sound through analysis of RLCR (Relative Level Crossing Rate) and spectrogram energy algorithm. Partial discharge diagnostic system has a function that stores PD sound and analyzes the data. The wave shape of PD sound is similar to noise and is systematically generated by partial discharge. Therefore, in this paper, we could discreminate between normal and abnormal case using relative level crossing rate (RLCR) and spectrogram of frequency energy rate.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.138-140
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• 2007

A novel AC-DC switching technology is suggested without inductors for one-chip semiconductor. The suggested converter consists of a rectifier diodes, AC source level detector, switching control, detector of over-current and voltage, feedback controller and switching block, The key technology of the proposed AC-DC converting methode is detecting of the low level voltage for AC voltage, power control transistor and rectifying of DC level. The measurement results with commercial devices show that the converter has power efficiency of 66.5% for DC 12V 0.24A and the standby power is 49.58mW at AC 110V.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.500-506
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• 1999

This paper presents the h밍h performance [GBT type auxiliary jXlWer supply designt.'Cl by new concept. For t the simplification and higher performance, the direct :3 level PWlVl inverter using the high capacity IGBT and t the 32bit DSP are adopted. The cost as well as bulk and weight is appreciably reduced about 40% lower than t those of conventional one. the electrical efficiency above 94~) o and the audible noise level is less than 65dB. In a addition, the TIID(Total lIannonic Distortion) factor is below 5% an이 the voltage fluctuation on a transient s state is below 10%.w 10%.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.