• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.122-130
• /
• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.6 s.336
• /
• pp.67-74
• /
• 2005

In this paper, high LO-RF isolation W-band MIMIC single-balanced mixer was designed and fabricated using a branch line coupler and a $\lambda$/4 transmission line. The simulation results of the designed 94 GHz balun show return loss of -27.9 dB, coupling of -4.26 dB, and thru of -3.77 dB at 94 GHz, respectively. The isolation and phase difference were 23.5 dB and $180.2^{\circ}$ at 94 GHz. The W-band MIMIC single-balanced mixer was designed using the 0.1 $\mu$m InGaAs/InAlAs/GaAs Metamorphic HEMT diode. The fabricated MHEMT was obtained the cut-off frequency(fT) of 189 GHz and the maximum oscillation frequency(fmax) of 334 GHz. The designed MIMIC single-balanced mixer was fabricated using 0.1 $\mu$m MHEMT MIMIC Process. From the measurement, the conversion loss of the single-balanced mixer was 23.1 dB at an LO power of 10 dBm. Pl dB(1 dB compression point) of input and output were 10 dBm and -13.9 dBm respectively. The LO-RF isolations of single-balanced mixer was obtained 45.5 dB at 94.19 GHz. We obtained in this study a higher LO-RF isolation compared to some other balanced mixers in millimeter-wave frequencies.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.87-97
• /
• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.7-14
• /
• 2009

In this paper, the effects of annealing conditions on the structural ((002) intensity, FWHM, d-spacing, grain size, (002) peak position), optical (UV peak, UV peak position) and electrical properties (carrier concentrations, resistivity, mobility) of ZnO films were investigated. ZnO films were deposited onto SiO$_2$/si substrates by RF magnetron sputtering from a ZnO target. The substrate was not heated during deposition. ZnO films were annealed in temperature ranges of $500\sim650^{\circ}C$ in the O$_2$ flow for 5$\sim$20 min. The film average thicknesses were in the range of 291 nm. The surface morphologies and structures of the samples were characterize by SEM and XRD, respectively. The optical properties were evaluated by photoluminescence (PL) measurement at room temperature (RT) using a He-Cd 325 nm laser. As the annealing temperature and time vary, the following relations were also observed: (1) proportional relationships among UV intensity (002) intensity, and grain size exist, (2) UV intensity is inversely proportional to FWHM, (3) there is no special relationship between UV intensity and electron carrier concentrations, (4) d-spacing is inversely proportional to (002) peak position, (5) UV peak position in the range of 3.20$\sim$3.24 eV means that ZnO films have a n-type conductivity which was consistent with that obtained from the electrical property, (6) the optimal conditions for the best optical and structural characteristics were found to be oxygen fraction, (O$_2$/(O$_2$+Ar)) of 0.2, RF power of 240W, substrate temperature of RT, annealing condition of 600$^{\circ}C$ for 20 min, and sputtering pressure of 20 mTorr.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.21-31
• /
• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.25-33
• /
• 2007

In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.3
• /
• pp.46-55
• /
• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of Animal Environmental Science
• /
• v.13 no.2
• /
• pp.113-120
• /
• 2007

This study was conducted to measure Nitrogen(N), Phosphate($P_2O_5$), Potassium ($K_2O$), Organic matter(OM) and Moisture content of liquid pig manure by Near Infrared Spectroscopy(NIRS) and to develop an alternative and analytical instrument which are used for measurement of N, $P_2O_5$, $K_2O$, OM, and Moisture contents for liquid pig manure. The liquid pig manure sample's transmittance spectra were measured with a NIRS in the wavelength range of 400 to 2,500 nm. Multiple linear regression and partial least square regression were used for calibrations. The correlation coefficient(RSQ) and standard error of calibration(SEC) obtained for nitrogen were 0.9190 and 2.1649, respectively. The RSQ for phosphate, potassium, organic matter and moisture contents were 0.9749, 0.5046, 0.9883 and 0.9777, and the SEC were 0.5019, 1.9252, 0.1180 and 0.0789, respectively. These results are indications of the rapid determination of components of liquid pig manure through the NIR analysis. The simple analytical instrument for liquid pig manure consisted of a tungsten halogen lamp for light source, a sample holder, a quartz cell, a SM 301 spectrometer for spectrum analyzer, a power supply, an electronics, a computer and a software. Results showed that the simple analytical instrument that was developed can approximately predict the phosphate, organic matter and moisture content of the liquid pig manure when compared to the analysis taken by NIRS. The low predictability value of potassium however, needs further investigation. Generally, the experiment proved that the simple analytical instrument was reliable, feasible and practical for analyzing liquid pig manure.

• Journal of Animal Environmental Science
• /
• v.10 no.3
• /
• pp.141-154
• /
• 2004

The solar powered water pump is very ideal equipment because solar power is more intensive when the water is more needed in summer and it is very helpful in the rural area, in which the electrical power is not available. The average so]ar radiation energy is 3.488 kWh/($m^2{\cdot}day$) in Korea. In this study, the automatic control logic and system of the water pump driven by the radiation energy were studied, designed, assembled, tested and analyzed for realizing the solar powered water pump. The experimental system was operated automatically and the cycle was continued. The average quantity of the water pumped per cycle was about 5,320 cc. The cycle time was about 4.9 minutes. The thermal efficiency of the system was about $0.030\%$. The pressure level of the n-pentane vapour in flash tank was 150$\%$450 hPa(gauge) which was set by the computer program for the control of the vapour supply. The pressure in the condenser and air tank during cycles was maintained as about 600 hPa and 1,200 hPa respectively. The water could be pumped by the amount of 128kg/($m^2{\cdot}day$) with the efficiency of $0.1\%$ and the pumping head of 10 m for the average solar energy in Korea.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.670-680
• /
• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.